[
    {
        "BriefDescription": "ASSISTS.PAGE_FAULT",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc1",
        "EventName": "ASSISTS.PAGE_FAULT",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
        "Counter": "0,1,2,3,4,5,6,7",
        "Deprecated": "1",
        "EventCode": "0xe4",
        "EventName": "LBR_INSERTS.ANY",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000001",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000002",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xa5",
        "EventName": "RS.EMPTY",
        "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
        "SampleAfterValue": "1000003",
        "UMask": "0x7",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
        "Counter": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xa5",
        "EventName": "RS.EMPTY_COUNT",
        "Invert": "1",
        "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
        "SampleAfterValue": "100003",
        "UMask": "0x7",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when RS was empty and a resource allocation stall is asserted",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xa5",
        "EventName": "RS.EMPTY_RESOURCE",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x75",
        "EventName": "SERIALIZATION.C01_MS_SCB",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cycles the uncore cannot take further requests",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x2d",
        "EventName": "XQ.FULL_CYCLES",
        "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    }
]