Lines Matching full:tiled

289  * packed YCbCr420 2x2 tiled formats
459  * of the data in a plane of an FB.  This can be used to express tiled/
542  * and so might actually result in a tiled framebuffer.
561  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
578  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
596  * This is a tiled layout using 4Kb tiles in row-major layout.
612  * The main surface will be plane index 0 and must be Y/Yf-tiled,
631  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
642  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
656  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
674  * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
787  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
802  * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
804  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
824  * Qualcomm Tiled Format
837  * Qualcomm Alternate Tiled Format
839  * Alternate tiled format typically only used within GMEM.
850  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
858  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
872  * compared to the non-split tiled layout.
881  * therefore halved compared to the non-split super-tiled layout.
917  * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
1123  * and UV.  Some SAND-using hardware stores UV in a separate tiled
1259  * AFBC tiled layout
1261  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1265  * When the tiled layout is used, the buffer size (in pixels) must be aligned
1419  * Allwinner tiled modifier
1524  * MediaTek Tiled Modifier
1553  * Apple GPU-tiled layouts.
1557  * GPU-tiled images are divided into 16KiB tiles: