Lines Matching full:surface

609  * Intel color control surface (CCS) for render compression
612  * The main surface will be plane index 0 and must be Y/Yf-tiled,
615  * Each CCS tile matches a 1024x512 pixel area of the main surface.
631  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
633  * main surface. In other words, 4 bits in CCS map to a main surface cache
634  * line pair. The main surface pitch is required to be a multiple of four
642  * The main surface is Y-tiled and at plane index 0, the CCS is linear and
644  * main surface. In other words, 4 bits in CCS map to a main surface cache
645  * line pair. The main surface pitch is required to be a multiple of four
653  * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
656  * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
666  * corresponds to an area of 4x1 tiles in the main surface. The main surface
685  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
688  * main surface pitch is required to be a multiple of four Tile 4 widths.
695  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
699  * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
705  * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
707  * The main surface is Tile 4 and at plane index 0. The CCS data is stored
710  * main surface pitch is required to be a multiple of four Tile 4 widths. The
721  * The main surface is tile4 and at plane index 0, the CCS is linear and
723  * main surface. In other words, 4 bits in CCS map to a main surface cache
724  * line pair. The main surface pitch is required to be a multiple of four
732  * The main surface is tile4 and at plane index 0, the CCS is linear and
734  * main surface. In other words, 4 bits in CCS map to a main surface cache
735  * line pair. The main surface pitch is required to be a multiple of four
743  * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
746  * The main surface is tile4 and is at plane index 0 whereas CCS is linear
756  * corresponds to an area of 4x1 tiles in the main surface. The main surface
765  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
777  * The main surface is Tile 4 and at plane index 0. For semi-planar formats
1602  *   - main surface
1605  *   - main surface in plane 0
1606  *   - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1609  *   - main surface in plane 0
1610  *   - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1611  *   - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1712  * DCC supports embedding some clear colors directly in the DCC surface.