Lines Matching +full:super +full:- +full:frames
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
225 * Half-Floating point - 16b/component
226 * IEEE 754-2008 binary16 half-precision float
240 * Floating point - 32b/component
241 * IEEE 754-2008 binary32 float
250 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
266 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
270 * 16-xx padding occupy lsb
278 * 16-xx padding occupy lsb except Y410
303 * 1-plane YUV 4:2:0
306 * These formats can only be used with a non-Linear modifier.
336 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
337 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
345 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
382 /* 3 plane non-subsampled (444) YCbCr
390 /* 3 plane non-subsampled (444) YCrCb
409 #define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */
422 #define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */
432 #define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */
451 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
452 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
458 * Format modifiers describe, typically, a re-ordering or modification
462 * The upper 8 bits of the format modifier are a vendor-id as assigned
483 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
503 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
505 * compatibility, in cases where a vendor-specific definition already exists and
510 * generic layouts (such as pixel re-ordering), which may have
511 * independently-developed support across multiple vendors.
514 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
541 * which tells the driver to also take driver-internal information into account
551 * used is out-of-band information carried in an API-specific way (e.g. in a
559 * Intel X-tiling layout
562 * in row-major layout. Within the tile bytes are laid out row-major, with
563 * a platform-dependent stride. On top of that the memory can apply
564 * platform-depending swizzling of some higher address bits into bit6.
568 * cross-driver sharing. It exists since on a given platform it does uniquely
569 * identify the layout in a simple way for i915-specific userspace, which
576 * Intel Y-tiling layout
579 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
580 * chunks column-major, with a platform-dependent height. On top of that the
581 * memory can apply platform-depending swizzling of some higher address bits
586 * cross-driver sharing. It exists since on a given platform it does uniquely
587 * identify the layout in a simple way for i915-specific userspace, which
594 * Intel Yf-tiling layout
596 * This is a tiled layout using 4Kb tiles in row-major layout.
597 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
598 * are arranged in four groups (two wide, two high) with column-major layout.
600 * out as 2x2 column-major.
612 * The main surface will be plane index 0 and must be Y/Yf-tiled,
629 * Intel color control surfaces (CCS) for Gen-12 render compression.
631 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
635 * Y-tile widths.
640 * Intel color control surfaces (CCS) for Gen-12 media compression
642 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
646 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
653 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
656 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
674 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
695 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
736 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
765 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
777 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
787 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
789 * Macroblocks are laid in a Z-shape, and each pixel data is following the
794 * - multiple of 128 pixels for the width
795 * - multiple of 32 pixels for the height
797 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
802 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
804 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
814 * Implementation may be platform and base-format specific.
827 * Implementation may be platform and base-format specific.
840 * Implementation may be platform and base-format specific.
850 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
856 * Vivante 64x64 super-tiling layout
858 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
859 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
863 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
868 * Vivante 4x4 tiling layout for dual-pipe
872 * compared to the non-split tiled layout.
877 * Vivante 64x64 super-tiling layout for dual-pipe
879 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
881 * therefore halved compared to the non-split super-tiled layout.
886 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
938 * ---- ----- -----------------------------------------------------------------
942 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
944 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
946 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
948 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
956 * 11:9 - Reserved (To support 2D-array textures with variable array stride
977 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
978 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
988 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
1004 * 55:25 - Reserved for future use. Must be zero.
1016 * with block-linear layouts, is remapped within drivers to the value 0xfe,
1017 * which corresponds to the "generic" kind used for simple single-sample
1018 * uncompressed color formats on Fermi - Volta GPUs.
1035 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1078 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1080 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1089 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1092 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1095 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1099 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1100 * tiles) or right-to-left (odd rows of 4k tiles).
1123 * and UV. Some SAND-using hardware stores UV in a separate tiled
1167 * the assumption is that a no-XOR tiling modifier will be created.
1175 * It provides fine-grained random access and minimizes the amount of data
1180 * and different devices or use-cases may support different combinations.
1212 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1229 * AFBC block-split
1250 * AFBC copy-block restrict
1252 * Buffers with this flag must obey the copy-block restriction. The restriction
1253 * is such that there are no copy-blocks referring across the border of 8x8
1273 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1279 * AFBC double-buffer
1281 * Indicates that the buffer is allocated in a layout safe for front-buffer
1289 * Indicates that the buffer includes per-superblock content hints.
1306 * Arm Fixed-Rate Compression (AFRC) modifiers
1310 * reductions in graphics and media use-cases.
1326 * ---------------- ---------------
1337 * ------ ----------------- ------------------
1346 * ----------------------------- --------- ----------------- ------------------
1349 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1350 * ----------------------------- --------- ----------------- ------------------
1353 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1354 * ----------------------------- --------- ----------------- ------------------
1356 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1357 * ----------------------------- --------- ----------------- ------------------
1360 * ----------------------------- --------- ----------------- ------------------
1379 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1384 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1386 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1388 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1402 * Indicates if the buffer uses the scanline-optimised layout
1403 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1409 * Arm 16x16 Block U-Interleaved modifier
1428 * both in row-major order.
1440 * frames in memory.
1442 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1444 * - DRM_FORMAT_YUV420_8BIT
1445 * - DRM_FORMAT_YUV420_10BIT
1469 * - a body content organized in 64x32 superblocks with 4096 bytes per
1471 * - a 32 bytes per 128x64 header block
1481 * frames content to optimize memory access and layout.
1489 * be accessible by the user-space clients, but only accessible by the
1492 * The user-space clients should expect a failure while trying to mmap
1493 * the DMA-BUF handle returned by the producer.
1514 * ----- ------------------------ ---------------------------------------------
1534 * Bits 8-15 specify compression options
1541 * Bits 16-23 specify how the bits of 10 bit formats are
1553 * Apple GPU-tiled layouts.
1557 * GPU-tiled images are divided into 16KiB tiles:
1560 * --------------- ---------
1567 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1569 * Compressed images pad the body to 128-bytes and are immediately followed by a
1571 * powers-of-two and contains 8 bytes for each 16x16 compression subtile.
1574 * All images are 128-byte aligned.
1591 * https://docs.mesa3d.org/drivers/asahi.html#image-layouts
1602 * - main surface
1605 * - main surface in plane 0
1606 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1609 * - main surface in plane 0
1610 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1611 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1613 * For multi-plane formats the above surfaces get merged into one plane for
1617 * ----- ------------------------ ---------------------------------------------
1633 * 55:36 - Reserved for future use, must be zero
1653 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1666 * 0 - LINEAR
1667 * 1 - 256B_2D - 2D block dimensions
1668 * 2 - 4KB_2D
1669 * 3 - 64KB_2D
1670 * 4 - 256KB_2D
1671 * 5 - 4KB_3D - 3D block dimensions
1672 * 6 - 64KB_3D
1673 * 7 - 256KB_3D
1695 * one which is not-aligned.