Lines Matching +full:4 +full:a
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
69 * a canonical pair needs to be defined and used by all drivers. Preferred
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
116 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
125 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */
126 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
137 /* 4 bpp Red (direct relationship between channel value and brightness) */
138 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
147 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
165 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
166 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
167 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
168 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
189 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
190 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
214 #define DRM_FORMAT_RGB161616 fourcc_code('R', 'G', '4', '8') /* [47:0] R:G:B 16:16:16 little endian */
215 #define DRM_FORMAT_BGR161616 fourcc_code('B', 'G', '4', '8') /* [47:0] B:G:R 16:16:16 little endian */
218 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
219 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
221 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
222 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
229 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
230 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
232 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
233 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
247 #define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 little endian */
253 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
261 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
262 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
265 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
273 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
280 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
281 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
282 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
285 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
286 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
290 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
303 * 1-plane YUV 4:2:0
306 * These formats can only be used with a non-Linear modifier.
312 * 2 plane RGB + A
314 * index 1 = A plane, [7:0] A
316 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
317 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
318 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
319 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
320 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
321 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
322 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
323 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
336 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
337 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
363 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
364 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
376 * 3 10 bit components and 2 padding bits packed into 4 bytes.
388 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
396 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
400 * In order to use these formats in a similar fashion to MSB aligned ones
409 #define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */
413 * In order to use these formats in a similar fashion to MSB aligned ones
414 * implementation can multiply the values by 2^4=16. For that reason the padding
416 * index 0 = Y plane, [15:0] z:Y [4:12] little endian
417 * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian
418 * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian
422 #define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */
432 #define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */
443 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
444 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
445 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
446 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
451 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
452 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
458 * Format modifiers describe, typically, a re-ordering or modification
459 * of the data in a plane of an FB. This can be used to express tiled/
460 * swizzled formats, or compression, or a combination of the two.
462 * The upper 8 bits of the format modifier are a vendor-id as assigned
497 * When adding a new token please document the layout with a code comment,
505 * compatibility, in cases where a vendor-specific definition already exists and
506 * a generic name for it is desired, the common name is a purely symbolic alias
513 * In future cases where a generic layout is identified before merging with a
514 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
517 * apply to a single vendor.
530 * This modifier can be used as a sentinel to terminate the format modifiers
531 * list, or to initialize a variable with an invalid modifier. It might also be
542 * and so might actually result in a tiled framebuffer.
551 * used is out-of-band information carried in an API-specific way (e.g. in a
561 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
563 * a platform-dependent stride. On top of that the memory can apply
568 * cross-driver sharing. It exists since on a given platform it does uniquely
569 * identify the layout in a simple way for i915-specific userspace, which
578 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
580 * chunks column-major, with a platform-dependent height. On top of that the
586 * cross-driver sharing. It exists since on a given platform it does uniquely
587 * identify the layout in a simple way for i915-specific userspace, which
596 * This is a tiled layout using 4Kb tiles in row-major layout.
602 * either a square block or a 2:1 unit.
615 * Each CCS tile matches a 1024x512 pixel area of the main surface.
620 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
625 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
632 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
633 * main surface. In other words, 4 bits in CCS map to a main surface cache
634 * line pair. The main surface pitch is required to be a multiple of four
643 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
644 * main surface. In other words, 4 bits in CCS map to a main surface cache
645 * line pair. The main surface pitch is required to be a multiple of four
665 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
666 * corresponds to an area of 4x1 tiles in the main surface. The main surface
667 * pitch is required to be a multiple of 4 tile widths.
672 * Intel Tile 4 layout
674 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
675 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
677 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
685 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
686 * outside of the GEM object in a reserved memory area dedicated for the
688 * main surface pitch is required to be a multiple of four Tile 4 widths.
695 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
696 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
698 * GEM object in a reserved memory area dedicated for the storage of the
700 * pitch is required to be a multiple of four Tile 4 widths.
707 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
708 * outside of the GEM object in a reserved memory area dedicated for the
710 * main surface pitch is required to be a multiple of four Tile 4 widths. The
722 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
723 * main surface. In other words, 4 bits in CCS map to a main surface cache
724 * line pair. The main surface pitch is required to be a multiple of four
733 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
734 * main surface. In other words, 4 bits in CCS map to a main surface cache
735 * line pair. The main surface pitch is required to be a multiple of four
755 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
756 * corresponds to an area of 4x1 tiles in the main surface. The main surface
757 * pitch is required to be a multiple of 4 tile widths.
765 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
766 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
768 * GEM object in a reserved memory area dedicated for the storage of the
777 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
778 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
780 * GEM object in a reserved memory area dedicated for the storage of the
782 * contiguous memory with a size aligned to 64KB
789 * Macroblocks are laid in a Z-shape, and each pixel data is following the
804 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
805 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
813 * Refers to a compressed variant of the base format that is compressed.
816 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
819 * Entire pixel data buffer is aligned with 4k(bytes).
829 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
832 * Entire pixel data buffer is aligned with 4k(bytes).
848 * Vivante 4x4 tiling layout
850 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
858 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
859 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
868 * Vivante 4x4 tiling layout for dual-pipe
870 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
879 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
880 * starts at a different base address. Offsets from the base addresses are
883 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
887 * the color buffer tiling modifiers defined above. When TS is present it's a
899 #define VIVANTE_MOD_TS_256_4 (4ULL << 48)
903 * Vivante compression modifiers. Those depend on a TS modifier being present
917 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
929 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
931 * a block depth or height of "4").
944 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
952 * hardware support a block width of two gobs, but it is impractical
960 * 19:12 k Page Kind. This value directly maps to a field in the page
973 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
978 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
982 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
999 * 4 = CDE vertical
1033 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
1035 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1044 * 4 == SIXTEEN_GOBS
1062 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
1089 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1092 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1095 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1096 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
1099 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1100 * tiles) or right-to-left (odd rows of 4k tiles).
1123 * and UV. Some SAND-using hardware stores UV in a separate tiled
1129 * wide, but as this is a 10 bpp format that translates to 96 pixels.
1137 fourcc_mod_broadcom_code(4, v)
1157 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
1166 * necessary to reduce the padding. If a hardware block can't do XOR,
1167 * the assumption is that a no-XOR tiling modifier will be created.
1174 * AFBC is a proprietary lossless image compression protocol and format.
1187 * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
1189 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1205 * size (in pixels) must be aligned to a multiple of the superblock size.
1218 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
1226 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
1232 * half of the payload is positioned at a predefined offset from the start
1240 * This flag indicates that the payload of each superblock must be stored at a
1261 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1262 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1263 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
1274 * can be reduced if a whole superblock is a single color.
1281 * Indicates that the buffer is allocated in a layout safe for front-buffer
1299 * affects the storage mode of the individual superblocks. Note that even a
1308 * AFRC is a proprietary fixed rate image compression protocol and format,
1316 * "coding unit" blocks which are individually compressed to a
1317 * fixed size (in bytes). All coding units within a given plane of a buffer
1332 * to a multiple of the paging tile dimensions.
1338 * SCAN 16 coding units 4 coding units
1347 * 1 SCAN 16 samples 4 samples
1348 * Example: 16x4 luma samples in a 'Y' plane
1349 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1352 * Example: 8x8 luma samples in a 'Y' plane
1353 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1355 * 2 DONT CARE 8 samples 4 samples
1356 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1358 * 3 DONT CARE 4 samples 4 samples
1359 * Example: 4x4 pixels in an RGB buffer without alpha
1361 * 4 DONT CARE 4 samples 4 samples
1362 * Example: 4x4 pixels in an RGB buffer with alpha
1397 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
1422 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1435 * Amlogic uses a proprietary lossless image compression protocol and format
1469 * - a body content organized in 64x32 superblocks with 4096 bytes per
1471 * - a 32 bytes per 128x64 header block
1492 * The user-space clients should expect a failure while trying to mmap
1563 * 4 64x64
1567 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1569 * Compressed images pad the body to 128-bytes and are immediately followed by a
1586 * software as a single plane. This is modelled after AFBC, a similar
1643 #define AMD_FMT_MOD_TILE_VER_GFX11 4
1668 * 2 - 4KB_2D
1670 * 4 - 256KB_2D
1671 * 5 - 4KB_3D - 3D block dimensions
1678 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
1714 * and prefers the driver provided color. This necessitates doing a fastclear
1715 * eliminate operation before a process transfers control.