Lines Matching +full:2 +full:- +full:a
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
69 * a canonical pair needs to be defined and used by all drivers. Preferred
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
115 #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byt…
122 /* 2 bpp Darkness (inverse relationship between channel value and brightness) */
123 #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byt…
134 /* 2 bpp Red (direct relationship between channel value and brightness) */
135 #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byt…
147 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
157 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
158 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
161 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
162 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
165 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian…
166 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian…
167 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian…
168 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian…
170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
189 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
190 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
203 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little …
204 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little …
205 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little …
206 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little …
208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
221 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 littl…
222 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 littl…
225 * Half-Floating point - 16b/component
226 * IEEE 754-2008 binary16 half-precision float
232 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
233 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
240 * Floating point - 32b/component
241 * IEEE 754-2008 binary32 float
247 #define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] R:G:B:A 32:32:32:32 lit…
250 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
253 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 1…
261 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
262 #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endi…
265 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
266 …010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only …
270 * 16-xx padding occupy lsb
272 …AT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:…
273 …AT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:…
274 …DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little…
278 * 16-xx padding occupy lsb except Y410
280 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
281 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12…
282 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
284 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 littl…
289 * packed YCbCr420 2x2 tiled formats
290 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
292 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
294 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little end…
298 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
300 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
303 * 1-plane YUV 4:2:0
306 * These formats can only be used with a non-Linear modifier.
312 * 2 plane RGB + A
314 * index 1 = A plane, [7:0] A
316 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
317 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
318 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
319 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
320 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
321 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
322 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
323 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
326 * 2 plane YCbCr
332 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
333 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
334 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
335 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
336 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
337 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
339 * 2 plane YCbCr
343 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
344 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
345 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
348 * 2 plane YCbCr MSB aligned
352 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per …
355 * 2 plane YCbCr MSB aligned
359 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
362 * 2 plane YCbCr MSB aligned
366 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per …
369 * 2 plane YCbCr MSB aligned
373 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per …
375 /* 2 plane YCbCr420.
376 * 3 10 bit components and 2 padding bits packed into 4 bytes.
377 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
378 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
380 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
382 /* 3 plane non-subsampled (444) YCbCr
386 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
390 /* 3 plane non-subsampled (444) YCrCb
394 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
400 * In order to use these formats in a similar fashion to MSB aligned ones
401 * implementation can multiply the values by 2^6=64. For that reason the padding
405 * index 2 = Cr plane, [15:0] z:Cr [6:10] little endian
407 #define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes …
408 #define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes …
409 #define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes …
413 * In order to use these formats in a similar fashion to MSB aligned ones
414 * implementation can multiply the values by 2^4=16. For that reason the padding
418 * index 2 = Cr plane, [15:0] z:Cr [4:12] little endian
420 #define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes …
421 #define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes …
422 #define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes …
428 * index 2 = Cr plane, [15:0] Cr little endian
430 #define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes …
431 #define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes …
432 #define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes …
438 * index 2: Cr plane, [7:0] Cr
441 * index 2: Cb plane, [7:0] Cb
443 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) plane…
444 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) plane…
445 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) plane…
446 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) plane…
447 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) plane…
448 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) plane…
449 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) plane…
450 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) plane…
451 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
452 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
458 * Format modifiers describe, typically, a re-ordering or modification
459 * of the data in a plane of an FB. This can be used to express tiled/
460 * swizzled formats, or compression, or a combination of the two.
462 * The upper 8 bits of the format modifier are a vendor-id as assigned
483 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
497 * When adding a new token please document the layout with a code comment,
503 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
505 * compatibility, in cases where a vendor-specific definition already exists and
506 * a generic name for it is desired, the common name is a purely symbolic alias
510 * generic layouts (such as pixel re-ordering), which may have
511 * independently-developed support across multiple vendors.
513 * In future cases where a generic layout is identified before merging with a
514 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
517 * apply to a single vendor.
530 * This modifier can be used as a sentinel to terminate the format modifiers
531 * list, or to initialize a variable with an invalid modifier. It might also be
541 * which tells the driver to also take driver-internal information into account
542 * and so might actually result in a tiled framebuffer.
551 * used is out-of-band information carried in an API-specific way (e.g. in a
559 * Intel X-tiling layout
561 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
562 * in row-major layout. Within the tile bytes are laid out row-major, with
563 * a platform-dependent stride. On top of that the memory can apply
564 * platform-depending swizzling of some higher address bits into bit6.
568 * cross-driver sharing. It exists since on a given platform it does uniquely
569 * identify the layout in a simple way for i915-specific userspace, which
576 * Intel Y-tiling layout
578 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
579 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
580 * chunks column-major, with a platform-dependent height. On top of that the
581 * memory can apply platform-depending swizzling of some higher address bits
586 * cross-driver sharing. It exists since on a given platform it does uniquely
587 * identify the layout in a simple way for i915-specific userspace, which
591 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
594 * Intel Yf-tiling layout
596 * This is a tiled layout using 4Kb tiles in row-major layout.
597 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
598 * are arranged in four groups (two wide, two high) with column-major layout.
600 * out as 2x2 column-major.
602 * either a square block or a 2:1 unit.
612 * The main surface will be plane index 0 and must be Y/Yf-tiled,
615 * Each CCS tile matches a 1024x512 pixel area of the main surface.
620 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
629 * Intel color control surfaces (CCS) for Gen-12 render compression.
631 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
632 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
633 * main surface. In other words, 4 bits in CCS map to a main surface cache
634 * line pair. The main surface pitch is required to be a multiple of four
635 * Y-tile widths.
640 * Intel color control surfaces (CCS) for Gen-12 media compression
642 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
643 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
644 * main surface. In other words, 4 bits in CCS map to a main surface cache
645 * line pair. The main surface pitch is required to be a multiple of four
646 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
648 * planes 2 and 3 for the respective CCS.
653 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
656 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
657 * and at index 1. The clear color is stored at index 2, and the pitch should
665 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
667 * pitch is required to be a multiple of 4 tile widths.
674 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
677 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
686 * outside of the GEM object in a reserved memory area dedicated for the
688 * main surface pitch is required to be a multiple of four Tile 4 widths.
695 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
698 * GEM object in a reserved memory area dedicated for the storage of the
700 * pitch is required to be a multiple of four Tile 4 widths.
708 * outside of the GEM object in a reserved memory area dedicated for the
710 * main surface pitch is required to be a multiple of four Tile 4 widths. The
722 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
723 * main surface. In other words, 4 bits in CCS map to a main surface cache
724 * line pair. The main surface pitch is required to be a multiple of four
733 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
734 * main surface. In other words, 4 bits in CCS map to a main surface cache
735 * line pair. The main surface pitch is required to be a multiple of four
736 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
738 * planes 2 and 3 for the respective CCS.
747 * and at index 1. The clear color is stored at index 2, and the pitch should
755 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
757 * pitch is required to be a multiple of 4 tile widths.
765 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
768 * GEM object in a reserved memory area dedicated for the storage of the
777 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
780 * GEM object in a reserved memory area dedicated for the storage of the
782 * contiguous memory with a size aligned to 64KB
787 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
789 * Macroblocks are laid in a Z-shape, and each pixel data is following the
792 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
794 * - multiple of 128 pixels for the width
795 * - multiple of 32 pixels for the height
797 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
802 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
804 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
805 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
808 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
813 * Refers to a compressed variant of the base format that is compressed.
814 * Implementation may be platform and base-format specific.
827 * Implementation may be platform and base-format specific.
840 * Implementation may be platform and base-format specific.
842 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
850 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
856 * Vivante 64x64 super-tiling layout
858 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
859 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
863 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
865 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
868 * Vivante 4x4 tiling layout for dual-pipe
870 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
872 * compared to the non-split tiled layout.
877 * Vivante 64x64 super-tiling layout for dual-pipe
879 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
880 * starts at a different base address. Offsets from the base addresses are
881 * therefore halved compared to the non-split super-tiled layout.
886 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
887 * the color buffer tiling modifiers defined above. When TS is present it's a
897 #define VIVANTE_MOD_TS_64_2 (2ULL << 48)
903 * Vivante compression modifiers. Those depend on a TS modifier being present
917 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
929 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
930 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
931 * a block depth or height of "4").
938 * ---- ----- -----------------------------------------------------------------
942 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
944 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
946 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
948 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
952 * hardware support a block width of two gobs, but it is impractical
956 * 11:9 - Reserved (To support 2D-array textures with variable array stride
960 * 19:12 k Page Kind. This value directly maps to a field in the page
973 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
977 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
978 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
979 * 2 = Gob Height 8, Turing+ Page Kind mapping
982 * 22:22 s Sector layout. There is a further bit remapping step that occurs
988 * 0 = Tegra K1 - Tegra Parker/TX2 Layout
989 * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout
990 * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout
991 * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout
1002 * 2 = ROP/3D, layout 2, exact compression format implied by Page
1010 * 55:28 - Reserved for future use. Must be zero.
1023 * with block-linear layouts, is remapped within drivers to the value 0xfe,
1024 * which corresponds to the "generic" kind used for simple single-sample
1025 * uncompressed color formats on Fermi - Volta GPUs.
1040 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
1042 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1049 * 2 == FOUR_GOBS
1065 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
1085 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1087 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1096 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1099 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1102 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1106 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1107 * tiles) or right-to-left (odd rows of 4k tiles).
1130 * and UV. Some SAND-using hardware stores UV in a separate tiled
1136 * wide, but as this is a 10 bpp format that translates to 96 pixels.
1140 fourcc_mod_broadcom_code(2, v)
1163 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
1173 * necessary to reduce the padding. If a hardware block can't do XOR,
1174 * the assumption is that a no-XOR tiling modifier will be created.
1181 * AFBC is a proprietary lossless image compression protocol and format.
1182 * It provides fine-grained random access and minimizes the amount of data
1187 * and different devices or use-cases may support different combinations.
1196 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1212 * size (in pixels) must be aligned to a multiple of the superblock size.
1219 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1223 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
1236 * AFBC block-split
1239 * half of the payload is positioned at a predefined offset from the start
1247 * This flag indicates that the payload of each superblock must be stored at a
1257 * AFBC copy-block restrict
1259 * Buffers with this flag must obey the copy-block restriction. The restriction
1260 * is such that there are no copy-blocks referring across the border of 8x8
1269 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1280 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1281 * can be reduced if a whole superblock is a single color.
1286 * AFBC double-buffer
1288 * Indicates that the buffer is allocated in a layout safe for front-buffer
1296 * Indicates that the buffer includes per-superblock content hints.
1306 * affects the storage mode of the individual superblocks. Note that even a
1313 * Arm Fixed-Rate Compression (AFRC) modifiers
1315 * AFRC is a proprietary fixed rate image compression protocol and format,
1317 * reductions in graphics and media use-cases.
1323 * "coding unit" blocks which are individually compressed to a
1324 * fixed size (in bytes). All coding units within a given plane of a buffer
1333 * ---------------- ---------------
1339 * to a multiple of the paging tile dimensions.
1344 * ------ ----------------- ------------------
1353 * ----------------------------- --------- ----------------- ------------------
1355 * Example: 16x4 luma samples in a 'Y' plane
1356 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1357 * ----------------------------- --------- ----------------- ------------------
1359 * Example: 8x8 luma samples in a 'Y' plane
1360 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1361 * ----------------------------- --------- ----------------- ------------------
1362 * 2 DONT CARE 8 samples 4 samples
1363 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1364 * ----------------------------- --------- ----------------- ------------------
1367 * ----------------------------- --------- ----------------- ------------------
1386 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1391 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1393 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1395 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1400 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
1409 * Indicates if the buffer uses the scanline-optimised layout
1410 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1416 * Arm 16x16 Block U-Interleaved modifier
1429 * into 64k byte 1:1 or 2:1 -sided tiles. The 64k tiles are laid out linearly.
1431 * themselves laid out linearly within a 64k tile. Then within each 16x16
1436 * depending on whether a format is compressed or not.
1439 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 2ULL)
1445 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1451 * both in row-major order.
1458 * Amlogic uses a proprietary lossless image compression protocol and format
1465 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1467 * - DRM_FORMAT_YUV420_8BIT
1468 * - DRM_FORMAT_YUV420_10BIT
1492 * - a body content organized in 64x32 superblocks with 4096 bytes per
1494 * - a 32 bytes per 128x64 header block
1512 * be accessible by the user-space clients, but only accessible by the
1515 * The user-space clients should expect a failure while trying to mmap
1516 * the DMA-BUF handle returned by the producer.
1518 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1537 * ----- ------------------------ ---------------------------------------------
1557 * Bits 8-15 specify compression options
1564 * Bits 16-23 specify how the bits of 10 bit formats are
1576 * Apple GPU-tiled layouts.
1580 * GPU-tiled images are divided into 16KiB tiles:
1583 * --------------- ---------
1585 * 2 128x64
1590 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1592 * Compressed images pad the body to 128-bytes and are immediately followed by a
1594 * powers-of-two and contains 8 bytes for each 16x16 compression subtile.
1597 * All images are 128-byte aligned.
1609 * software as a single plane. This is modelled after AFBC, a similar
1614 * https://docs.mesa3d.org/drivers/asahi.html#image-layouts
1617 #define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)
1625 * - main surface
1628 * - main surface in plane 0
1629 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1632 * - main surface in plane 0
1633 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1634 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1636 * For multi-plane formats the above surfaces get merged into one plane for
1640 * ----- ------------------------ ---------------------------------------------
1656 * 55:36 - Reserved for future use, must be zero
1664 #define AMD_FMT_MOD_TILE_VER_GFX10 2
1676 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1689 * 0 - LINEAR
1690 * 1 - 256B_2D - 2D block dimensions
1691 * 2 - 4KB_2D
1692 * 3 - 64KB_2D
1693 * 4 - 256KB_2D
1694 * 5 - 4KB_3D - 3D block dimensions
1695 * 6 - 64KB_3D
1696 * 7 - 256KB_3D
1699 #define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
1705 #define AMD_FMT_MOD_DCC_BLOCK_256B 2
1718 * one which is not-aligned.
1737 * and prefers the driver provided color. This necessitates doing a fastclear
1738 * eliminate operation before a process transfers control.