Lines Matching +full:10 +full:bits
143 /* 10 bpp Red (direct relationship between channel value and brightness) */
144 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
203 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little …
204 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little …
205 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little …
206 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little …
208 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
209 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
210 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
211 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
227 * [15:0] sign:exponent:mantissa 1:5:10
250 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
253 …106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little end…
266 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. N…
272 … fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little end…
280 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
284 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 littl…
290 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
297 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
299 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
349 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
350 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
352 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per …
356 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
357 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
359 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
366 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per …
373 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per …
376 * 3 10 bit components and 2 padding bits packed into 4 bytes.
377 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
378 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
380 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per …
383 * 16 bits per component, but only 10 bits are used and 6 bits are padded
384 * index 0: Y plane, [15:0] Y:x [10:6] little endian
385 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
386 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
391 * 16 bits per component, but only 10 bits are used and 6 bits are padded
392 * index 0: Y plane, [15:0] Y:x [10:6] little endian
393 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
394 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
403 * index 0 = Y plane, [15:0] z:Y [6:10] little endian
404 * index 1 = Cb plane, [15:0] z:Cb [6:10] little endian
405 * index 2 = Cr plane, [15:0] z:Cr [6:10] little endian
407 …0 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
408 …0 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
409 …0 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */
420 …2 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
421 …2 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
422 …2 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */
430 …6 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
431 …6 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
432 …6 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */
462 * The upper 8 bits of the format modifier are a vendor-id as assigned
463 * below. The lower 56 bits are assigned as vendor sees fit.
564 * platform-depending swizzling of some higher address bits into bit6.
581 * memory can apply platform-depending swizzling of some higher address bits
633 * main surface. In other words, 4 bits in CCS map to a main surface cache
644 * main surface. In other words, 4 bits in CCS map to a main surface cache
658 * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
660 * by 32 bits. The raw clear color is consumed by the 3d engine and generates
661 * the converted clear color of size 64 bits. The first 32 bits store the Lower
662 * Converted Clear Color value and the next 32 bits store the Higher Converted
664 * consumed by the DE. The last 64 bits are used to store Color Discard Enable
690 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
712 * aligned. The format of the 256 bits of clear color data matches the one used
723 * main surface. In other words, 4 bits in CCS map to a main surface cache
734 * main surface. In other words, 4 bits in CCS map to a main surface cache
748 * be ignored. The clear color structure is 256 bits. The first 128 bits
750 * by 32 bits. The raw clear color is consumed by the 3d engine and generates
751 * the converted clear color of size 64 bits. The first 32 bits store the Lower
752 * Converted Clear Color value and the next 32 bits store the Higher Converted
754 * consumed by the DE. The last 64 bits are used to store Color Discard Enable
891 * number of status bits per entry.
892 * We reserve the top 8 bits of the Vivante modifier space for tile status
904 * as the TS bits get reinterpreted as compression tags instead of simple
910 /* Masking out the extension bits will yield the base modifier. */
937 * Bits Param Description
961 * tables of all GPUs >= NV50. It affects the exact layout of bits
1075 * vertical lines in the image. Reserve the lower 32 bits for modifier
1076 * type, and the next 24 bits for parameters. Top 8 bits are the
1136 * wide, but as this is a 10 bpp format that translates to 96 pixels.
1186 * represented using bits in the modifier. Not all combinations are valid,
1194 * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
1213 * Four lowest significant bits(LSBs) are reserved for block size.
1291 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1465 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1470 * The first 8 bits of the mode defines the layout, then the following 8 bits
1536 * Bits Parameter Notes
1540 * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*
1548 * The lowest 8 bits of the modifier is used to specify the tiling
1557 * Bits 8-15 specify compression options
1564 * Bits 16-23 specify how the bits of 10 bit formats are
1639 * Bits Parameter Notes
1681 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10