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4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
8 * and/or sell copies of the Software, and to permit persons to whom the
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
46 * format and data layout of the buffer, and should be the only way to describe
50 * be avoided, as such aliases run the risk of different drivers exposing
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
62 * match only a single modifier. A modifier must not be a subset of layouts of
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
68 * For modifiers where the combination of fourcc code and modifier can alias,
74 * There are two kinds of modifier users:
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
83 * (i.e. they are not expected to extract information out of the modifier).
89 * The authoritative list of format modifier codes is found in
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
108 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
114 #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
116 #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
119 /* 1 bpp Darkness (inverse relationship between channel value and brightness) */
120 #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
125 /* 4 bpp Darkness (inverse relationship between channel value and brightness) */
126 #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
131 /* 1 bpp Red (direct relationship between channel value and brightness) */
132 #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
137 /* 4 bpp Red (direct relationship between channel value and brightness) */
138 #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
144 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
147 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
150 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
165 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
166 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
167 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
168 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
170 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
171 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
172 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
173 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
175 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
176 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
177 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
178 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
180 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
181 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
182 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
183 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
185 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
186 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
189 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
190 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
193 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
194 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
195 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
196 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
198 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
199 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
200 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
201 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
214 #define DRM_FORMAT_RGB161616 fourcc_code('R', 'G', '4', '8') /* [47:0] R:G:B 16:16:16 little endian */
215 #define DRM_FORMAT_BGR161616 fourcc_code('B', 'G', '4', '8') /* [47:0] B:G:R 16:16:16 little endian */
218 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
219 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
221 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
222 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
225 * Half-Floating point - 16b/component
226 * IEEE 754-2008 binary16 half-precision float
227 * [15:0] sign:exponent:mantissa 1:5:10
229 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
230 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
232 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
233 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
240 * Floating point - 32b/component
241 * IEEE 754-2008 binary32 float
242 * [31:0] sign:exponent:mantissa 1:8:23
250 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
251 * of unused padding per component:
253 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
265 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
266 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
270 * 16-xx padding occupy lsb
272 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
273 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
274 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
278 * 16-xx padding occupy lsb except Y410
280 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
281 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
282 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
285 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
286 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
292 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
294 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
297 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
299 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
303 * 1-plane YUV 4:2:0
306 * These formats can only be used with a non-Linear modifier.
309 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
314 * index 1 = A plane, [7:0] A
328 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
330 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
332 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
333 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
334 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
335 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
336 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
337 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
341 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
343 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
345 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
350 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
352 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
357 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
359 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
363 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
364 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
366 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
371 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
373 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
376 * 3 10 bit components and 2 padding bits packed into 4 bytes.
378 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
382 /* 3 plane non-subsampled (444) YCbCr
385 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
388 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
390 /* 3 plane non-subsampled (444) YCrCb
393 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
396 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
404 * index 1 = Cr plane, [15:0] z:Cr [6:10] little endian
407 #define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
408 #define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */
409 #define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */
414 * implementation can multiply the values by 2^4=16. For that reason the padding
416 * index 0 = Y plane, [15:0] z:Y [4:12] little endian
417 * index 1 = Cr plane, [15:0] z:Cr [4:12] little endian
418 * index 2 = Cb plane, [15:0] z:Cb [4:12] little endian
420 #define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
421 #define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */
422 #define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */
427 * index 1 = Cr plane, [15:0] Cr little endian
430 #define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
431 #define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */
432 #define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */
437 * index 1: Cb plane, [7:0] Cb
440 * index 1: Cr plane, [7:0] Cr
443 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
444 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
445 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
446 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
447 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
448 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
449 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
450 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
451 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
452 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
458 * Format modifiers describe, typically, a re-ordering or modification
459 * of the data in a plane of an FB. This can be used to express tiled/
460 * swizzled formats, or compression, or a combination of the two.
462 * The upper 8 bits of the format modifier are a vendor-id as assigned
483 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
499 * authoritative source for all of these.
503 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
505 * compatibility, in cases where a vendor-specific definition already exists and
510 * generic layouts (such as pixel re-ordering), which may have
511 * independently-developed support across multiple vendors.
514 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
520 * have implementations of the same standardised compression scheme (such as
522 * modifier(s), reflecting the vendor of the standard.
541 * which tells the driver to also take driver-internal information into account
551 * used is out-of-band information carried in an API-specific way (e.g. in a
559 * Intel X-tiling layout
561 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
562 * in row-major layout. Within the tile bytes are laid out row-major, with
563 * a platform-dependent stride. On top of that the memory can apply
564 * platform-depending swizzling of some higher address bits into bit6.
568 * cross-driver sharing. It exists since on a given platform it does uniquely
569 * identify the layout in a simple way for i915-specific userspace, which
570 * facilitated conversion of userspace to modifiers. Additionally the exact
573 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
576 * Intel Y-tiling layout
578 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
579 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
580 * chunks column-major, with a platform-dependent height. On top of that the
581 * memory can apply platform-depending swizzling of some higher address bits
586 * cross-driver sharing. It exists since on a given platform it does uniquely
587 * identify the layout in a simple way for i915-specific userspace, which
588 * facilitated conversion of userspace to modifiers. Additionally the exact
594 * Intel Yf-tiling layout
596 * This is a tiled layout using 4Kb tiles in row-major layout.
597 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
598 * are arranged in four groups (two wide, two high) with column-major layout.
599 * Each group therefore consists out of four 256 byte units, which are also laid
600 * out as 2x2 column-major.
601 * 256 byte units are made out of four 64 byte blocks of pixels, producing
602 * either a square block or a 2:1 unit.
603 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
611 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
612 * The main surface will be plane index 0 and must be Y/Yf-tiled,
613 * the CCS will be plane index 1.
615 * Each CCS tile matches a 1024x512 pixel area of the main surface.
616 * To match certain aspects of the 3D hardware the CCS is
617 * considered to be made up of normal 128Bx32 Y tiles, Thus
618 * the CCS pitch must be specified in multiples of 128 bytes.
621 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
625 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
629 * Intel color control surfaces (CCS) for Gen-12 render compression.
631 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
632 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
633 * main surface. In other words, 4 bits in CCS map to a main surface cache
634 * line pair. The main surface pitch is required to be a multiple of four
635 * Y-tile widths.
640 * Intel color control surfaces (CCS) for Gen-12 media compression
642 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
643 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
644 * main surface. In other words, 4 bits in CCS map to a main surface cache
645 * line pair. The main surface pitch is required to be a multiple of four
646 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
647 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
653 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
656 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
657 * and at index 1. The clear color is stored at index 2, and the pitch should
661 * the converted clear color of size 64 bits. The first 32 bits store the Lower
666 * corresponds to an area of 4x1 tiles in the main surface. The main surface
667 * pitch is required to be a multiple of 4 tile widths.
672 * Intel Tile 4 layout
674 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
675 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
677 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
678 * of 64B x 8 rows.
685 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
686 * outside of the GEM object in a reserved memory area dedicated for the
687 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
688 * main surface pitch is required to be a multiple of four Tile 4 widths.
695 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
696 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
697 * 0 and 1, respectively. The CCS for all planes are stored outside of the
698 * GEM object in a reserved memory area dedicated for the storage of the
700 * pitch is required to be a multiple of four Tile 4 widths.
707 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
708 * outside of the GEM object in a reserved memory area dedicated for the
709 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
710 * main surface pitch is required to be a multiple of four Tile 4 widths. The
711 * clear color is stored at plane index 1 and the pitch should be 64 bytes
712 * aligned. The format of the 256 bits of clear color data matches the one used
722 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
723 * main surface. In other words, 4 bits in CCS map to a main surface cache
724 * line pair. The main surface pitch is required to be a multiple of four
733 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
734 * main surface. In other words, 4 bits in CCS map to a main surface cache
735 * line pair. The main surface pitch is required to be a multiple of four
736 * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
737 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
747 * and at index 1. The clear color is stored at index 2, and the pitch should
751 * the converted clear color of size 64 bits. The first 32 bits store the Lower
756 * corresponds to an area of 4x1 tiles in the main surface. The main surface
757 * pitch is required to be a multiple of 4 tile widths.
765 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
766 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
767 * 0 and 1, respectively. The CCS for all planes are stored outside of the
768 * GEM object in a reserved memory area dedicated for the storage of the
777 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
778 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
779 * 0 and 1, respectively. The CCS for all planes are stored outside of the
780 * GEM object in a reserved memory area dedicated for the storage of the
787 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
789 * Macroblocks are laid in a Z-shape, and each pixel data is following the
791 * As for NV12, an image is the result of two frame buffers: one for Y,
792 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
794 * - multiple of 128 pixels for the width
795 * - multiple of 32 pixels for the height
797 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
799 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
802 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
804 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
813 * Refers to a compressed variant of the base format that is compressed.
814 * Implementation may be platform and base-format specific.
816 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
819 * Entire pixel data buffer is aligned with 4k(bytes).
821 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
827 * Implementation may be platform and base-format specific.
829 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
832 * Entire pixel data buffer is aligned with 4k(bytes).
840 * Implementation may be platform and base-format specific.
848 * Vivante 4x4 tiling layout
850 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
853 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
856 * Vivante 64x64 super-tiling layout
858 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
859 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
863 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
868 * Vivante 4x4 tiling layout for dual-pipe
870 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
872 * compared to the non-split tiled layout.
877 * Vivante 64x64 super-tiling layout for dual-pipe
879 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
881 * therefore halved compared to the non-split super-tiled layout.
883 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
886 * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
888 * separate buffer containing the clear/compression status of each tile. The
891 * number of status bits per entry.
892 * We reserve the top 8 bits of the Vivante modifier space for tile status
896 #define VIVANTE_MOD_TS_64_4 (1ULL << 48)
899 #define VIVANTE_MOD_TS_256_4 (4ULL << 48)
904 * as the TS bits get reinterpreted as compression tags instead of simple
907 #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52)
917 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
919 * Pixels are arranged in simple tiles of 16 x 16 bytes.
921 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
927 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
929 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
930 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
931 * a block depth or height of "4").
933 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
938 * ---- ----- -----------------------------------------------------------------
940 * 3:0 h log2(height) of each block, in GOBs. Placed here for
942 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
944 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
946 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
948 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
951 * Note there is no log2(width) parameter. Some portions of the
952 * hardware support a block width of two gobs, but it is impractical
953 * to use due to lack of support elsewhere, and has no known
956 * 11:9 - Reserved (To support 2D-array textures with variable array stride
961 * tables of all GPUs >= NV50. It affects the exact layout of bits
969 * since the modifier should define the layout of the associated
973 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
977 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
978 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
984 * page kind and block linear swizzles. This causes the layout of
988 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
989 * 1 = Desktop GPU and Tegra Xavier+ Layout
994 * 1 = ROP/3D, layout 1, exact compression format implied by Page
999 * 4 = CDE vertical
1004 * 55:25 - Reserved for future use. Must be zero.
1016 * with block-linear layouts, is remapped within drivers to the value 0xfe,
1017 * which corresponds to the "generic" kind used for simple single-sample
1018 * uncompressed color formats on Fermi - Volta GPUs.
1032 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
1033 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
1035 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
1037 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
1041 * 1 == TWO_GOBS
1044 * 4 == SIXTEEN_GOBS
1047 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
1056 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
1062 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
1067 * Some Broadcom modifiers take parameters, for example the number of
1078 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
1080 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
1089 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
1092 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
1095 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
1096 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
1097 * they're (TR, BR, BL, TL), where bottom left is start of memory.
1099 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
1100 * tiles) or right-to-left (odd rows of 4k tiles).
1102 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
1111 * columns are placed consecutively into memory. The width of those
1115 * The pitch between the start of each column is set to optimally
1116 * switch between SDRAM banks. This is passed as the number of lines
1117 * of column width in the modifier (we can't use the stride value due
1122 * for all of the planes, assuming that each column contains both Y
1123 * and UV. Some SAND-using hardware stores UV in a separate tiled
1137 fourcc_mod_broadcom_code(4, v)
1156 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
1157 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
1164 * number of banks, and XOR address, and that it's identical between
1167 * the assumption is that a no-XOR tiling modifier will be created.
1175 * It provides fine-grained random access and minimizes the amount of data
1180 * and different devices or use-cases may support different combinations.
1182 * Further information on the use of AFBC modifiers can be found in
1187 * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
1189 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
1205 * size (in pixels) must be aligned to a multiple of the superblock size.
1208 * Where one superblock size is specified, it applies to all planes of the
1212 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1215 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
1218 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
1223 * Indicates that the buffer makes use of the AFBC lossless colorspace
1226 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
1229 * AFBC block-split
1231 * Indicates that the payload of each superblock is split. The second
1232 * half of the payload is positioned at a predefined offset from the start
1233 * of the superblock payload.
1235 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
1240 * This flag indicates that the payload of each superblock must be stored at a
1243 * each superblock is given the same amount of space as an uncompressed
1244 * superblock of the particular format would require, rounding up to the next
1245 * multiple of 128 bytes in size.
1247 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
1250 * AFBC copy-block restrict
1252 * Buffers with this flag must obey the copy-block restriction. The restriction
1253 * is such that there are no copy-blocks referring across the border of 8x8
1256 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
1261 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1263 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
1268 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1273 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1276 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
1279 * AFBC double-buffer
1281 * Indicates that the buffer is allocated in a layout safe for front-buffer
1284 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1289 * Indicates that the buffer includes per-superblock content hints.
1291 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1299 * affects the storage mode of the individual superblocks. Note that even a
1303 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1306 * Arm Fixed-Rate Compression (AFRC) modifiers
1310 * reductions in graphics and media use-cases.
1312 * AFRC buffers consist of one or more planes, with the same components
1317 * fixed size (in bytes). All coding units within a given plane of a buffer
1318 * store the same number of values, and have the same compressed size.
1320 * The coding unit size is configurable, allowing different rates of compression.
1322 * The start of each AFRC buffer plane must be aligned to an alignment granule which
1326 * ---------------- ---------------
1332 * to a multiple of the paging tile dimensions.
1333 * The dimensions of each paging tile depend on whether the buffer is optimised for
1337 * ------ ----------------- ------------------
1338 * SCAN 16 coding units 4 coding units
1341 * The dimensions of each coding unit depend on the number of components
1345 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
1346 * ----------------------------- --------- ----------------- ------------------
1347 * 1 SCAN 16 samples 4 samples
1349 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1350 * ----------------------------- --------- ----------------- ------------------
1351 * 1 ROT 8 samples 8 samples
1353 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1354 * ----------------------------- --------- ----------------- ------------------
1355 * 2 DONT CARE 8 samples 4 samples
1356 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1357 * ----------------------------- --------- ----------------- ------------------
1358 * 3 DONT CARE 4 samples 4 samples
1359 * Example: 4x4 pixels in an RGB buffer without alpha
1360 * ----------------------------- --------- ----------------- ------------------
1361 * 4 DONT CARE 4 samples 4 samples
1362 * Example: 4x4 pixels in an RGB buffer with alpha
1373 * Indicates the number of bytes used to store each compressed coding unit for
1377 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
1378 * each compressed coding unit in the first plane of the buffer. For RGBA buffers
1379 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1382 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
1384 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1386 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1388 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1392 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1397 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
1402 * Indicates if the buffer uses the scanline-optimised layout
1403 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1406 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1409 * Arm 16x16 Block U-Interleaved modifier
1416 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1428 * both in row-major order.
1430 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1442 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1444 * - DRM_FORMAT_YUV420_8BIT
1445 * - DRM_FORMAT_YUV420_10BIT
1447 * The first 8 bits of the mode defines the layout, then the following 8 bits
1451 * combinations of layout and options.
1468 * The basic layout is composed of:
1469 * - a body content organized in 64x32 superblocks with 4096 bytes per
1471 * - a 32 bytes per 128x64 header block
1475 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1488 * Due to the nature of the layout, these buffers are not expected to
1489 * be accessible by the user-space clients, but only accessible by the
1492 * The user-space clients should expect a failure while trying to mmap
1493 * the DMA-BUF handle returned by the producer.
1502 * Indicates the storage is packed when pixel size is multiple of word
1510 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1514 * ----- ------------------------ ---------------------------------------------
1525 * The lowest 8 bits of the modifier is used to specify the tiling
1534 * Bits 8-15 specify compression options
1541 * Bits 16-23 specify how the bits of 10 bit formats are
1553 * Apple GPU-tiled layouts.
1557 * GPU-tiled images are divided into 16KiB tiles:
1560 * --------------- ---------
1561 * 1 128x128
1563 * 4 64x64
1567 * Tiles are raster-order. Pixels within a tile are interleaved (Morton order).
1569 * Compressed images pad the body to 128-bytes and are immediately followed by a
1571 * powers-of-two and contains 8 bytes for each 16x16 compression subtile.
1574 * All images are 128-byte aligned.
1577 * specify strides for these layouts, userspace unaware of Apple image layouts
1579 * Userspace aware of the image layouts do not use strides. The most "correct"
1591 * https://docs.mesa3d.org/drivers/asahi.html#image-layouts
1593 #define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)
1602 * - main surface
1605 * - main surface in plane 0
1606 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1609 * - main surface in plane 0
1610 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1611 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1613 * For multi-plane formats the above surfaces get merged into one plane for
1617 * ----- ------------------------ ---------------------------------------------
1633 * 55:36 - Reserved for future use, must be zero
1640 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1643 #define AMD_FMT_MOD_TILE_VER_GFX11 4
1653 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1666 * 0 - LINEAR
1667 * 1 - 256B_2D - 2D block dimensions
1668 * 2 - 4KB_2D
1669 * 3 - 64KB_2D
1670 * 4 - 256KB_2D
1671 * 5 - 4KB_3D - 3D block dimensions
1672 * 6 - 64KB_3D
1673 * 7 - 256KB_3D
1675 #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
1678 #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
1681 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1695 * one which is not-aligned.