1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
11  * QUICC Engine (QE).
30 #include <soc/fsl/qe/immap_qe.h>
31 #include <soc/fsl/qe/qe.h>
46 static u8 snums[QE_NUM_OF_SNUM];	/* Dynamically allocated SNUMs */  variable
50 static phys_addr_t qebase = -1;
54 	struct device_node *qe;  in qe_get_device_node()  local
57 	 * Newer device trees have an "fsl,qe" compatible property for the QE  in qe_get_device_node()
60 	qe = of_find_compatible_node(NULL, NULL, "fsl,qe");  in qe_get_device_node()
61 	if (qe)  in qe_get_device_node()
62 		return qe;  in qe_get_device_node()
63 	return of_find_node_by_type(NULL, "qe");  in qe_get_device_node()
68 	struct device_node *qe;  in get_qe_base()  local
72 	if (qebase != -1)  in get_qe_base()
75 	qe = qe_get_device_node();  in get_qe_base()
76 	if (!qe)  in get_qe_base()
79 	ret = of_address_to_resource(qe, 0, &res);  in get_qe_base()
82 	of_node_put(qe);  in get_qe_base()
113 		iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);  in qe_issue_cmd()
116 			/* Here device is the SNUM, not sub-block */  in qe_issue_cmd()
130 		iowrite32be(cmd_input, &qe_immr->cp.cecdr);  in qe_issue_cmd()
132 			       &qe_immr->cp.cecr);  in qe_issue_cmd()
136 	ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val,  in qe_issue_cmd()
138 	/* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */  in qe_issue_cmd()
146  * 16 BRGs, which can be connected to the QE channels or output
149  * The BRG clock is the QE clock divided by 2.
152  * Baud rate clocks are zero-based in the driver code (as that maps
153  * to port numbers). Documentation uses 1-based numbering.
162 	struct device_node *qe;  in qe_get_brg_clk()  local
169 	qe = qe_get_device_node();  in qe_get_brg_clk()
170 	if (!qe)  in qe_get_brg_clk()
173 	if (!of_property_read_u32(qe, "brg-frequency", &brg))  in qe_get_brg_clk()
176 	of_node_put(qe);  in qe_get_brg_clk()
182 			brg_clk -= mod;  in qe_get_brg_clk()
183 		else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))  in qe_get_brg_clk()
184 			brg_clk += CLK_GRAN - mod;  in qe_get_brg_clk()
204  * @brg: the BRG, QE_BRG1 - QE_BRG16
216 		return -EINVAL;  in qe_setbrg()
226 	   that the BRG divisor must be even if you're not using divide-by-16  in qe_setbrg()
232 	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |  in qe_setbrg()
235 	iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);  in qe_setbrg()
241 /* Convert a string to a QE clock source enum
262 			return (QE_BRG1 - 1) + i;  in qe_clock_source()
270 			return (QE_CLK1 - 1) + i;  in qe_clock_source()
279 /* Initialize SNUMs (thread serial numbers) according to
280  * QE Module Control chapter, SNUM table
304 	struct device_node *qe;  in qe_snums_init()  local
310 	qe = qe_get_device_node();  in qe_snums_init()
311 	if (qe) {  in qe_snums_init()
312 		i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",  in qe_snums_init()
313 						       snums, 1, QE_NUM_OF_SNUM);  in qe_snums_init()
315 			of_node_put(qe);  in qe_snums_init()
321 		 * fsl,qe-num-snums to choose one of the static arrays  in qe_snums_init()
324 		of_property_read_u32(qe, "fsl,qe-num-snums", &qe_num_of_snum);  in qe_snums_init()
325 		of_node_put(qe);  in qe_snums_init()
333 		pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n", qe_num_of_snum);  in qe_snums_init()
336 	memcpy(snums, snum_init, qe_num_of_snum);  in qe_snums_init()
342 	int snum = -EBUSY;  in qe_get_snum()
349 		snum = snums[i];  in qe_get_snum()
359 	const u8 *p = memchr(snums, snum, qe_num_of_snum);  in qe_put_snum()
362 		clear_bit(p - snums, snum_state);  in qe_put_snum()
368 	struct sdma __iomem *sdma = &qe_immr->sdma;  in qe_sdma_init()
369 	static s32 sdma_buf_offset = -ENOMEM;  in qe_sdma_init()
376 			return -ENOMEM;  in qe_sdma_init()
380 		       &sdma->sdebcr);  in qe_sdma_init()
382 		       &sdma->sdmr);  in qe_sdma_init()
394  * Set to 1 if QE firmware has been uploaded, and therefore
400  * Upload a QE microcode
408 	const __be32 *code = base + be32_to_cpu(ucode->code_offset);  in qe_upload_microcode()
411 	if (ucode->major || ucode->minor || ucode->revision)  in qe_upload_microcode()
412 		printk(KERN_INFO "qe-firmware: "  in qe_upload_microcode()
414 			ucode->id, ucode->major, ucode->minor, ucode->revision);  in qe_upload_microcode()
416 		printk(KERN_INFO "qe-firmware: "  in qe_upload_microcode()
417 			"uploading microcode '%s'\n", ucode->id);  in qe_upload_microcode()
419 	/* Use auto-increment */  in qe_upload_microcode()
420 	iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,  in qe_upload_microcode()
421 		       &qe_immr->iram.iadd);  in qe_upload_microcode()
423 	for (i = 0; i < be32_to_cpu(ucode->count); i++)  in qe_upload_microcode()
424 		iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);  in qe_upload_microcode()
426 	/* Set I-RAM Ready Register */  in qe_upload_microcode()
427 	iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);  in qe_upload_microcode()
431  * Upload a microcode to the I-RAM at a specific address.
433  * See Documentation/arch/powerpc/qe_firmware.rst for information on QE microcode
457 		printk(KERN_ERR "qe-firmware: invalid pointer\n");  in qe_upload_firmware()
458 		return -EINVAL;  in qe_upload_firmware()
461 	hdr = &firmware->header;  in qe_upload_firmware()
462 	length = be32_to_cpu(hdr->length);  in qe_upload_firmware()
465 	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||  in qe_upload_firmware()
466 	    (hdr->magic[2] != 'F')) {  in qe_upload_firmware()
467 		printk(KERN_ERR "qe-firmware: not a microcode\n");  in qe_upload_firmware()
468 		return -EPERM;  in qe_upload_firmware()
472 	if (hdr->version != 1) {  in qe_upload_firmware()
473 		printk(KERN_ERR "qe-firmware: unsupported version\n");  in qe_upload_firmware()
474 		return -EPERM;  in qe_upload_firmware()
478 	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {  in qe_upload_firmware()
479 		printk(KERN_ERR "qe-firmware: invalid data\n");  in qe_upload_firmware()
480 		return -EINVAL;  in qe_upload_firmware()
484 	calc_size = struct_size(firmware, microcode, firmware->count);  in qe_upload_firmware()
486 	for (i = 0; i < firmware->count; i++)  in qe_upload_firmware()
493 			be32_to_cpu(firmware->microcode[i].count);  in qe_upload_firmware()
497 		printk(KERN_ERR "qe-firmware: invalid length\n");  in qe_upload_firmware()
498 		return -EPERM;  in qe_upload_firmware()
504 		printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");  in qe_upload_firmware()
505 		return -EIO;  in qe_upload_firmware()
509 	 * If the microcode calls for it, split the I-RAM.  in qe_upload_firmware()
511 	if (!firmware->split)  in qe_upload_firmware()
512 		qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);  in qe_upload_firmware()
514 	if (firmware->soc.model)  in qe_upload_firmware()
516 			"qe-firmware: firmware '%s' for %u V%u.%u\n",  in qe_upload_firmware()
517 			firmware->id, be16_to_cpu(firmware->soc.model),  in qe_upload_firmware()
518 			firmware->soc.major, firmware->soc.minor);  in qe_upload_firmware()
520 		printk(KERN_INFO "qe-firmware: firmware '%s'\n",  in qe_upload_firmware()
521 			firmware->id);  in qe_upload_firmware()
524 	 * The QE only supports one microcode per RISC, so clear out all the  in qe_upload_firmware()
528 	strscpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));  in qe_upload_firmware()
529 	qe_firmware_info.extended_modes = be64_to_cpu(firmware->extended_modes);  in qe_upload_firmware()
530 	memcpy(qe_firmware_info.vtraps, firmware->vtraps,  in qe_upload_firmware()
531 		sizeof(firmware->vtraps));  in qe_upload_firmware()
534 	for (i = 0; i < firmware->count; i++) {  in qe_upload_firmware()
535 		const struct qe_microcode *ucode = &firmware->microcode[i];  in qe_upload_firmware()
538 		if (ucode->code_offset)  in qe_upload_firmware()
543 			u32 trap = be32_to_cpu(ucode->traps[j]);  in qe_upload_firmware()
547 					       &qe_immr->rsp[i].tibcr[j]);  in qe_upload_firmware()
551 		iowrite32be(be32_to_cpu(ucode->eccr),  in qe_upload_firmware()
552 			       &qe_immr->rsp[i].eccr);  in qe_upload_firmware()
562  * Get info on the currently-loaded firmware
570 	struct device_node *qe;  in qe_get_firmware_info()  local
586 	qe = qe_get_device_node();  in qe_get_firmware_info()
587 	if (!qe)  in qe_get_firmware_info()
591 	fw = of_get_child_by_name(qe, "firmware");  in qe_get_firmware_info()
592 	of_node_put(qe);  in qe_get_firmware_info()
606 	of_property_read_u64(fw, "extended-modes",  in qe_get_firmware_info()
609 	of_property_read_u32_array(fw, "virtual-traps", qe_firmware_info.vtraps,  in qe_get_firmware_info()
620 	struct device_node *qe;  in qe_get_num_of_risc()  local
623 	qe = qe_get_device_node();  in qe_get_num_of_risc()
624 	if (!qe)  in qe_get_num_of_risc()
627 	of_property_read_u32(qe, "fsl,qe-num-riscs", &num_of_risc);  in qe_get_num_of_risc()
629 	of_node_put(qe);  in qe_get_num_of_risc()
645 	np = of_find_compatible_node(NULL, NULL, "fsl,qe");  in qe_init()
647 		return -ENODEV;  in qe_init()
668 	{ .compatible = "fsl,qe", },
674 		.name = "fsl-qe",