8  * - Supports frequencies between 0.5Hz and 2048Hz with following steps:
9  *   - 0.5 Hz steps from 0.5 Hz to 32 Hz
10  *   - 2 Hz steps from 2 Hz to 128 Hz
11  *   - 8 Hz steps from 8 Hz to 512 Hz
12  *   - 32 Hz steps from 32 Hz to 2048 Hz
59 #define MC33XS2410_PWM_MAX_PERIOD(step)		(2000000000 >> (2 * (step)))
83 	return spi_write(spi, tx, len * 2);  in mc33xs2410_write_regs()
101 	t.len = len * 2;  in mc33xs2410_read_regs()
169 	case MC33XS2410_PWM_MAX_PERIOD(3) + 1 ... MC33XS2410_PWM_MAX_PERIOD(2):  in mc33xs2410_pwm_get_freq()
170 		step = 2;  in mc33xs2410_pwm_get_freq()
172 	case MC33XS2410_PWM_MAX_PERIOD(2) + 1 ... MC33XS2410_PWM_MAX_PERIOD(1):  in mc33xs2410_pwm_get_freq()
195 	 *   - 0 = 0.5Hz  in mc33xs2410_pwm_get_period()
196 	 *   - 1 = 2Hz  in mc33xs2410_pwm_get_period()
197 	 *   - 2 = 8Hz  in mc33xs2410_pwm_get_period()
198 	 *   - 3 = 32Hz  in mc33xs2410_pwm_get_period()
205 	doubled_steps = 1 << (FIELD_GET(MC33XS2410_PWM_FREQ_STEP, reg) * 2);  in mc33xs2410_pwm_get_period()
210 	return DIV_ROUND_UP(2 * NSEC_PER_SEC, doubled_freq);  in mc33xs2410_pwm_get_period()
233 	u16 rd_val[2];  in mc33xs2410_pwm_apply()
241 	ret = mc33xs2410_read_regs(spi, &reg[2], MC33XS2410_FRAME_IN_DATA_RD, rd_val, 2);  in mc33xs2410_pwm_apply()
263 		wr_val[2] = rd_val[0] | mask;  in mc33xs2410_pwm_apply()
265 		wr_val[2] = rd_val[0] & ~mask;  in mc33xs2410_pwm_apply()
298 	state->polarity = (val[2] & MC33XS2410_PWM_CTRL1_POL_INV(pwm->hwpwm + 1)) ?  in mc33xs2410_pwm_get_state()