1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
29 #define REG21_SEL_TX_CK_INV	BIT(7)
36 #define REG33_MODE_SET_DONE	BIT(7)
37 #define REG33_FIX_DA		BIT(1)
39 #define REG34_PHY_READY	BIT(7)
40 #define REG34_PLL_LOCK		BIT(6)
41 #define REG34_PHY_CLK_READY	BIT(5)
170 		.pll_div_regs = { 0xd1, 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 },
179 		.pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 },
185 		.pll_div_regs = { 0xd1, 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },
188 		.pll_div_regs = { 0xd1, 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 },
191 		.pll_div_regs = { 0xd1, 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 },
194 		.pll_div_regs = { 0xd1, 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },
197 		.pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },
286 	/* PHY_REG(1-7) pix clk specific */
296 	{ PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
332 	u32 pclk = cfg->pixclk;  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
345 		return -EINVAL;  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
347 	writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12));  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
354 	 *   2nd) Increase resolution to avoid rounding issues  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
365 	       phy->regs + PHY_REG(13));  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
366 	writeb(FIELD_PREP(REG14_TOL_MASK, 2) |  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
367 	       FIELD_PREP(REG14_RP_CODE_MASK, 2) |  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
369 	       phy->regs + PHY_REG(14));  in fsl_samsung_hdmi_phy_configure_pll_lock_det()
383 	 * Figure 13-78 of the reference manual states the PLL should be TMDS x 5  in fsl_samsung_hdmi_phy_find_pms()
405 			 * but it does show it as an 8-bit value, so reject  in fsl_samsung_hdmi_phy_find_pms()
415 			 * Rev 2 of the Ref Manual states the  in fsl_samsung_hdmi_phy_find_pms()
426 			/* Final frequency after post-divider */  in fsl_samsung_hdmi_phy_find_pms()
429 			delta = abs(fout - tmp);  in fsl_samsung_hdmi_phy_find_pms()
460 	writeb(REG33_FIX_DA, phy->regs + PHY_REG(33));  in fsl_samsung_hdmi_phy_configure()
464 		writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg);  in fsl_samsung_hdmi_phy_configure()
468 		writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(1) + i * 4);  in fsl_samsung_hdmi_phy_configure()
472 	       cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21));  in fsl_samsung_hdmi_phy_configure()
476 		dev_err(phy->dev, "pixclock too large\n");  in fsl_samsung_hdmi_phy_configure()
480 	writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));  in fsl_samsung_hdmi_phy_configure()
482 	ret = readb_poll_timeout(phy->regs + PHY_REG(34), val,  in fsl_samsung_hdmi_phy_configure()
485 		dev_err(phy->dev, "PLL failed to lock\n");  in fsl_samsung_hdmi_phy_configure()
495 	if (!phy->cur_cfg)  in phy_clk_recalc_rate()
498 	return phy->cur_cfg->pixclk;  in phy_clk_recalc_rate()
501 /* Helper function to lookup the available fractional-divider rate */
507 	for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)  in fsl_samsung_hdmi_phy_lookup_rate()
517 	cal_phy->pixclk = rate;  in fsl_samsung_hdmi_calculate_phy()
518 	cal_phy->pll_div_regs[0] = FIELD_PREP(REG01_PMS_P_MASK, p);  in fsl_samsung_hdmi_calculate_phy()
519 	cal_phy->pll_div_regs[1] = m;  in fsl_samsung_hdmi_calculate_phy()
520 	cal_phy->pll_div_regs[2] = FIELD_PREP(REG03_PMS_S_MASK, s-1);  in fsl_samsung_hdmi_calculate_phy()
521 	/* pll_div_regs 3-6 are fixed and pre-defined already */  in fsl_samsung_hdmi_calculate_phy()
528 	if (abs((long)rate - (long)int_div_clk) < abs((long)(rate - (long)frac_div_clk)))  in fsl_samsung_hdmi_phy_get_closest_rate()
544 		return -EINVAL;  in phy_clk_round_rate()
550 	if (rate == fract_div_phy->pixclk)  in phy_clk_round_rate()
551 		return fract_div_phy->pixclk;  in phy_clk_round_rate()
561 	return fract_div_phy->pixclk;  in phy_clk_round_rate()
566 	phy->cur_cfg = fract_div_phy;  in phy_use_fract_div()
567 	dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: using fractional divider rate = %u\n",  in phy_use_fract_div()
568 		phy->cur_cfg->pixclk);  in phy_use_fract_div()
569 	return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);  in phy_use_fract_div()
575 	phy->cur_cfg  = &calculated_phy_pll_cfg;  in phy_use_integer_div()
576 	dev_dbg(phy->dev, "fsl_samsung_hdmi_phy: integer divider rate = %u\n",  in phy_use_integer_div()
577 		phy->cur_cfg->pixclk);  in phy_use_integer_div()
578 	return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);  in phy_use_integer_div()
594 	if (fract_div_phy->pixclk == rate)  in phy_clk_set_rate()
611 						  fract_div_phy->pixclk) == fract_div_phy->pixclk)  in phy_clk_set_rate()
625 	struct device *dev = phy->dev;  in phy_clk_register()
626 	struct device_node *np = dev->of_node;  in phy_clk_register()
632 	parent_name = __clk_get_name(phy->refclk);  in phy_clk_register()
640 	phy->hw.init = &init;  in phy_clk_register()
642 	phyclk = devm_clk_register(dev, &phy->hw);  in phy_clk_register()
660 	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);  in fsl_samsung_hdmi_phy_probe()
662 		return -ENOMEM;  in fsl_samsung_hdmi_phy_probe()
665 	phy->dev = &pdev->dev;  in fsl_samsung_hdmi_phy_probe()
667 	phy->regs = devm_platform_ioremap_resource(pdev, 0);  in fsl_samsung_hdmi_phy_probe()
668 	if (IS_ERR(phy->regs))  in fsl_samsung_hdmi_phy_probe()
669 		return PTR_ERR(phy->regs);  in fsl_samsung_hdmi_phy_probe()
671 	phy->apbclk = devm_clk_get_enabled(phy->dev, "apb");  in fsl_samsung_hdmi_phy_probe()
672 	if (IS_ERR(phy->apbclk))  in fsl_samsung_hdmi_phy_probe()
673 		return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),  in fsl_samsung_hdmi_phy_probe()
676 	phy->refclk = devm_clk_get(phy->dev, "ref");  in fsl_samsung_hdmi_phy_probe()
677 	if (IS_ERR(phy->refclk))  in fsl_samsung_hdmi_phy_probe()
678 		return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),  in fsl_samsung_hdmi_phy_probe()
681 	pm_runtime_get_noresume(phy->dev);  in fsl_samsung_hdmi_phy_probe()
682 	pm_runtime_set_active(phy->dev);  in fsl_samsung_hdmi_phy_probe()
683 	pm_runtime_enable(phy->dev);  in fsl_samsung_hdmi_phy_probe()
687 		dev_err(&pdev->dev, "register clk failed\n");  in fsl_samsung_hdmi_phy_probe()
691 	pm_runtime_put(phy->dev);  in fsl_samsung_hdmi_phy_probe()
701 	of_clk_del_provider(pdev->dev.of_node);  in fsl_samsung_hdmi_phy_remove()
708 	clk_disable_unprepare(phy->apbclk);  in fsl_samsung_hdmi_phy_suspend()
718 	ret = clk_prepare_enable(phy->apbclk);  in fsl_samsung_hdmi_phy_resume()
720 		dev_err(phy->dev, "failed to enable apbclk\n");  in fsl_samsung_hdmi_phy_resume()
724 	if (phy->cur_cfg)  in fsl_samsung_hdmi_phy_resume()
725 		ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);  in fsl_samsung_hdmi_phy_resume()
737 		.compatible = "fsl,imx8mp-hdmi-phy",
748 		.name = "fsl-samsung-hdmi-phy",