Lines Matching full:aardvark

3  * Driver for the Aardvark PCIe controller, used on Marvell Armada
67 /* Aardvark Control registers */
520 	 * Note that this Aardvark PCI Bridge does not have compliant Type 1  in advk_pcie_setup_hw()
521 	 * Configuration Space and it even cannot be accessed via Aardvark's  in advk_pcie_setup_hw()
523 	 * available in internal Aardvark registers starting at offset 0x0  in advk_pcie_setup_hw()
528 	 * access to configuration space via internal Aardvark registers or  in advk_pcie_setup_hw()
729 		 * So return -EAGAIN and caller (pci-aardvark.c driver) will  in advk_pcie_check_pio_status()
872 		 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0.  in advk_pci_bridge_emul_pcie_conf_read()
1058 	 * Aardvark HW provides PCIe Capability structure in version 2 and  in advk_sw_pci_bridge_init()
1567 		 * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0.  in advk_pcie_handle_pme()
1621 		 * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use  in advk_pcie_handle_int()
1757 		 * Aardvark hardware allows to configure also PCIe window  in advk_pcie_probe()
1986 MODULE_DESCRIPTION("Aardvark PCIe controller");