Lines Matching defs:path
191 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
201 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
312 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
329 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
359 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
377 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
403 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
420 int path, i;
423 for (path = 0; path < 2; path++)
425 if (comp_addrs[path][i] == 0)
428 data = phycap_map[comp_addrs[path][i] - phycap_addr];
430 &gain->comp[path][i]);
581 enum rtw89_rf_path path)
592 reg = bb_gain_lna[i].gain_g[path];
594 reg = bb_gain_lna[i].gain_a[path];
597 val = gain->lna_gain[gain_band][path][i];
603 reg = bb_gain_tia[i].gain_g[path];
605 reg = bb_gain_tia[i].gain_a[path];
608 val = gain->tia_gain[gain_band][path][i];
648 u8 path;
653 for (path = RF_PATH_A; path < BB_PATH_NUM_8852BX; path++) {
654 tmp = efuse_gain->comp[path][subband];
656 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
806 static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
813 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
814 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
817 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
818 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
821 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
822 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
825 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
826 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
829 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
830 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
838 void rtw8852bt_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path)
855 rtw89_phy_write32_mask(rtwdev, idac2[path], B_P0_CFCH_CTL, 0x8);
856 rtw89_phy_write32_mask(rtwdev, rck_reset_count[path], B_ADCMOD_LP, 0x9);
857 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], B_WDADC_SEL, 0x2);
858 rtw89_phy_write32_mask(rtwdev, rx_adc_clk[path], B_P0_RXCK_ADJ, 0x49);
859 rtw89_phy_write32_mask(rtwdev, decim_filter[path], B_DCIM_FR, 0x0);
866 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2);
867 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x3);
868 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0xf);
869 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0);
874 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x2);
876 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
879 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2);
880 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2);
881 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x8);
882 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0);
883 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
888 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x0);
889 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2);
890 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x4);
891 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x6);
892 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
1236 /* @pwr_ofst (unit: 1/8 dBm): power of path A minus power of path B */
1349 sar_parm.path = RF_PATH_A;
1353 sar_parm.path = RF_PATH_B;
1791 void rtw8852bx_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1793 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
1794 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
1795 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
1796 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1823 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1976 u8 path;
1982 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
1983 status->chains |= BIT(path);
1984 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);