Lines Matching +full:rx +full:- +full:equalizer
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2018-2025 Intel Corporation
6 #include "iwl-trans.h"
7 #include "iwl-fh.h"
8 #include "iwl-context-info-v2.h"
10 #include "iwl-prph.h"
42 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_ctxt_info_dbg_enable()
46 if (fw_mon->size) { in iwl_pcie_ctxt_info_dbg_enable()
52 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical); in iwl_pcie_ctxt_info_dbg_enable()
53 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size); in iwl_pcie_ctxt_info_dbg_enable()
59 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_ctxt_info_dbg_enable()
61 switch (le32_to_cpu(fw_mon_cfg->buf_location)) { in iwl_pcie_ctxt_info_dbg_enable()
75 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) { in iwl_pcie_ctxt_info_dbg_enable()
77 &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_ctxt_info_dbg_enable()
79 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical); in iwl_pcie_ctxt_info_dbg_enable()
80 dbg_cfg->hwm_size = cpu_to_le32(frag->size); in iwl_pcie_ctxt_info_dbg_enable()
81 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset); in iwl_pcie_ctxt_info_dbg_enable()
84 dbg_cfg->debug_token_config); in iwl_pcie_ctxt_info_dbg_enable()
88 trans->dbg.fw_mon_ini[alloc_id].num_frags); in iwl_pcie_ctxt_info_dbg_enable()
93 le32_to_cpu(fw_mon_cfg->buf_location)); in iwl_pcie_ctxt_info_dbg_enable()
113 trans->mac_cfg->base->min_txq_size); in iwl_pcie_ctxt_info_v2_alloc()
115 switch (trans->conf.rx_buf_size) { in iwl_pcie_ctxt_info_v2_alloc()
117 return -EINVAL; in iwl_pcie_ctxt_info_v2_alloc()
135 if (trans->conf.dsbr_urm_fw_dependent) in iwl_pcie_ctxt_info_v2_alloc()
138 if (trans->conf.dsbr_urm_permanent) in iwl_pcie_ctxt_info_v2_alloc()
141 if (trans->conf.ext_32khz_clock_valid) in iwl_pcie_ctxt_info_v2_alloc()
145 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch), in iwl_pcie_ctxt_info_v2_alloc()
146 &trans_pcie->prph_scratch_dma_addr, in iwl_pcie_ctxt_info_v2_alloc()
149 return -ENOMEM; in iwl_pcie_ctxt_info_v2_alloc()
151 prph_sc_ctrl = &prph_scratch->ctrl_cfg; in iwl_pcie_ctxt_info_v2_alloc()
153 prph_sc_ctrl->version.version = 0; in iwl_pcie_ctxt_info_v2_alloc()
154 prph_sc_ctrl->version.mac_id = in iwl_pcie_ctxt_info_v2_alloc()
155 cpu_to_le16((u16)trans->info.hw_rev); in iwl_pcie_ctxt_info_v2_alloc()
156 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4); in iwl_pcie_ctxt_info_v2_alloc()
161 if (trans->mac_cfg->imr_enabled) in iwl_pcie_ctxt_info_v2_alloc()
164 if (CSR_HW_REV_TYPE(trans->info.hw_rev) == IWL_CFG_MAC_TYPE_GL && in iwl_pcie_ctxt_info_v2_alloc()
172 if (trans->do_top_reset) { in iwl_pcie_ctxt_info_v2_alloc()
173 WARN_ON(trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_SC); in iwl_pcie_ctxt_info_v2_alloc()
177 /* initialize RX default queue */ in iwl_pcie_ctxt_info_v2_alloc()
178 prph_sc_ctrl->rbd_cfg.free_rbd_addr = in iwl_pcie_ctxt_info_v2_alloc()
179 cpu_to_le64(trans_pcie->rxq->bd_dma); in iwl_pcie_ctxt_info_v2_alloc()
181 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg, in iwl_pcie_ctxt_info_v2_alloc()
183 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags); in iwl_pcie_ctxt_info_v2_alloc()
184 prph_sc_ctrl->control.control_flags_ext = cpu_to_le32(control_flags_ext); in iwl_pcie_ctxt_info_v2_alloc()
186 /* initialize the Step equalizer data */ in iwl_pcie_ctxt_info_v2_alloc()
187 prph_sc_ctrl->step_cfg.mbx_addr_0 = in iwl_pcie_ctxt_info_v2_alloc()
188 cpu_to_le32(trans->conf.mbx_addr_0_step); in iwl_pcie_ctxt_info_v2_alloc()
189 prph_sc_ctrl->step_cfg.mbx_addr_1 = in iwl_pcie_ctxt_info_v2_alloc()
190 cpu_to_le32(trans->conf.mbx_addr_1_step); in iwl_pcie_ctxt_info_v2_alloc()
193 ret = iwl_pcie_init_fw_sec(trans, img, &prph_scratch->dram.common); in iwl_pcie_ctxt_info_v2_alloc()
202 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't in iwl_pcie_ctxt_info_v2_alloc()
207 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE, in iwl_pcie_ctxt_info_v2_alloc()
208 &trans_pcie->prph_info_dma_addr, in iwl_pcie_ctxt_info_v2_alloc()
211 ret = -ENOMEM; in iwl_pcie_ctxt_info_v2_alloc()
216 ctxt_info_v2 = dma_alloc_coherent(trans->dev, in iwl_pcie_ctxt_info_v2_alloc()
218 &trans_pcie->ctxt_info_dma_addr, in iwl_pcie_ctxt_info_v2_alloc()
221 ret = -ENOMEM; in iwl_pcie_ctxt_info_v2_alloc()
225 ctxt_info_v2->prph_info_base_addr = in iwl_pcie_ctxt_info_v2_alloc()
226 cpu_to_le64(trans_pcie->prph_info_dma_addr); in iwl_pcie_ctxt_info_v2_alloc()
227 ctxt_info_v2->prph_scratch_base_addr = in iwl_pcie_ctxt_info_v2_alloc()
228 cpu_to_le64(trans_pcie->prph_scratch_dma_addr); in iwl_pcie_ctxt_info_v2_alloc()
236 sizeof(prph_scratch->dram.fseq_img) != in iwl_pcie_ctxt_info_v2_alloc()
239 ctxt_info_v2->prph_scratch_size = in iwl_pcie_ctxt_info_v2_alloc()
242 ctxt_info_v2->prph_scratch_size = in iwl_pcie_ctxt_info_v2_alloc()
246 ctxt_info_v2->cr_head_idx_arr_base_addr = in iwl_pcie_ctxt_info_v2_alloc()
247 cpu_to_le64(trans_pcie->rxq->rb_stts_dma); in iwl_pcie_ctxt_info_v2_alloc()
248 ctxt_info_v2->tr_tail_idx_arr_base_addr = in iwl_pcie_ctxt_info_v2_alloc()
249 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2); in iwl_pcie_ctxt_info_v2_alloc()
250 ctxt_info_v2->cr_tail_idx_arr_base_addr = in iwl_pcie_ctxt_info_v2_alloc()
251 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4); in iwl_pcie_ctxt_info_v2_alloc()
252 ctxt_info_v2->mtr_base_addr = in iwl_pcie_ctxt_info_v2_alloc()
253 cpu_to_le64(trans_pcie->txqs.txq[trans->conf.cmd_queue]->dma_addr); in iwl_pcie_ctxt_info_v2_alloc()
254 ctxt_info_v2->mcr_base_addr = in iwl_pcie_ctxt_info_v2_alloc()
255 cpu_to_le64(trans_pcie->rxq->used_bd_dma); in iwl_pcie_ctxt_info_v2_alloc()
256 ctxt_info_v2->mtr_size = in iwl_pcie_ctxt_info_v2_alloc()
258 ctxt_info_v2->mcr_size = in iwl_pcie_ctxt_info_v2_alloc()
261 trans_pcie->ctxt_info_v2 = ctxt_info_v2; in iwl_pcie_ctxt_info_v2_alloc()
262 trans_pcie->prph_info = prph_info; in iwl_pcie_ctxt_info_v2_alloc()
263 trans_pcie->prph_scratch = prph_scratch; in iwl_pcie_ctxt_info_v2_alloc()
266 trans_pcie->iml_len = fw->iml_len; in iwl_pcie_ctxt_info_v2_alloc()
267 trans_pcie->iml = dma_alloc_coherent(trans->dev, fw->iml_len, in iwl_pcie_ctxt_info_v2_alloc()
268 &trans_pcie->iml_dma_addr, in iwl_pcie_ctxt_info_v2_alloc()
270 if (!trans_pcie->iml) { in iwl_pcie_ctxt_info_v2_alloc()
271 ret = -ENOMEM; in iwl_pcie_ctxt_info_v2_alloc()
275 memcpy(trans_pcie->iml, fw->iml, fw->iml_len); in iwl_pcie_ctxt_info_v2_alloc()
280 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_v2), in iwl_pcie_ctxt_info_v2_alloc()
281 trans_pcie->ctxt_info_v2, in iwl_pcie_ctxt_info_v2_alloc()
282 trans_pcie->ctxt_info_dma_addr); in iwl_pcie_ctxt_info_v2_alloc()
283 trans_pcie->ctxt_info_v2 = NULL; in iwl_pcie_ctxt_info_v2_alloc()
285 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info, in iwl_pcie_ctxt_info_v2_alloc()
286 trans_pcie->prph_info_dma_addr); in iwl_pcie_ctxt_info_v2_alloc()
289 dma_free_coherent(trans->dev, in iwl_pcie_ctxt_info_v2_alloc()
292 trans_pcie->prph_scratch_dma_addr); in iwl_pcie_ctxt_info_v2_alloc()
301 iwl_enable_fw_load_int_ctx_info(trans, trans->do_top_reset); in iwl_pcie_ctxt_info_v2_kick()
304 iwl_write64(trans, CSR_CTXT_INFO_ADDR, trans_pcie->ctxt_info_dma_addr); in iwl_pcie_ctxt_info_v2_kick()
305 iwl_write64(trans, CSR_IML_DATA_ADDR, trans_pcie->iml_dma_addr); in iwl_pcie_ctxt_info_v2_kick()
306 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans_pcie->iml_len); in iwl_pcie_ctxt_info_v2_kick()
316 if (trans_pcie->iml) { in iwl_pcie_ctxt_info_v2_free()
317 dma_free_coherent(trans->dev, trans_pcie->iml_len, in iwl_pcie_ctxt_info_v2_free()
318 trans_pcie->iml, in iwl_pcie_ctxt_info_v2_free()
319 trans_pcie->iml_dma_addr); in iwl_pcie_ctxt_info_v2_free()
320 trans_pcie->iml_dma_addr = 0; in iwl_pcie_ctxt_info_v2_free()
321 trans_pcie->iml_len = 0; in iwl_pcie_ctxt_info_v2_free()
322 trans_pcie->iml = NULL; in iwl_pcie_ctxt_info_v2_free()
330 if (!trans_pcie->ctxt_info_v2) in iwl_pcie_ctxt_info_v2_free()
334 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_v2), in iwl_pcie_ctxt_info_v2_free()
335 trans_pcie->ctxt_info_v2, in iwl_pcie_ctxt_info_v2_free()
336 trans_pcie->ctxt_info_dma_addr); in iwl_pcie_ctxt_info_v2_free()
337 trans_pcie->ctxt_info_dma_addr = 0; in iwl_pcie_ctxt_info_v2_free()
338 trans_pcie->ctxt_info_v2 = NULL; in iwl_pcie_ctxt_info_v2_free()
340 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch), in iwl_pcie_ctxt_info_v2_free()
341 trans_pcie->prph_scratch, in iwl_pcie_ctxt_info_v2_free()
342 trans_pcie->prph_scratch_dma_addr); in iwl_pcie_ctxt_info_v2_free()
343 trans_pcie->prph_scratch_dma_addr = 0; in iwl_pcie_ctxt_info_v2_free()
344 trans_pcie->prph_scratch = NULL; in iwl_pcie_ctxt_info_v2_free()
347 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info, in iwl_pcie_ctxt_info_v2_free()
348 trans_pcie->prph_info_dma_addr); in iwl_pcie_ctxt_info_v2_free()
349 trans_pcie->prph_info_dma_addr = 0; in iwl_pcie_ctxt_info_v2_free()
350 trans_pcie->prph_info = NULL; in iwl_pcie_ctxt_info_v2_free()
359 if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) { in iwl_pcie_load_payloads_contig()
361 pnvm_data->n_chunks); in iwl_pcie_load_payloads_contig()
362 return -EINVAL; in iwl_pcie_load_payloads_contig()
365 len0 = pnvm_data->chunks[0].len; in iwl_pcie_load_payloads_contig()
366 len1 = pnvm_data->chunks[1].len; in iwl_pcie_load_payloads_contig()
367 if (len1 > 0xFFFFFFFF - len0) { in iwl_pcie_load_payloads_contig()
369 return -EINVAL; in iwl_pcie_load_payloads_contig()
373 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, in iwl_pcie_load_payloads_contig()
374 &dram->physical); in iwl_pcie_load_payloads_contig()
375 if (!dram->block) { in iwl_pcie_load_payloads_contig()
377 return -ENOMEM; in iwl_pcie_load_payloads_contig()
380 dram->size = len; in iwl_pcie_load_payloads_contig()
381 memcpy(dram->block, pnvm_data->chunks[0].data, len0); in iwl_pcie_load_payloads_contig()
382 memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1); in iwl_pcie_load_payloads_contig()
392 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0]; in iwl_pcie_load_payloads_segments()
393 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; in iwl_pcie_load_payloads_segments()
401 desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent in iwl_pcie_load_payloads_segments()
404 &desc_dram->physical); in iwl_pcie_load_payloads_segments()
405 if (!desc_dram->block) { in iwl_pcie_load_payloads_segments()
407 return -ENOMEM; in iwl_pcie_load_payloads_segments()
409 desc_dram->size = len; in iwl_pcie_load_payloads_segments()
410 memset(desc_dram->block, 0, len); in iwl_pcie_load_payloads_segments()
413 dram_regions->n_regions = 0; in iwl_pcie_load_payloads_segments()
414 for (i = 0; i < pnvm_data->n_chunks; i++) { in iwl_pcie_load_payloads_segments()
415 len = pnvm_data->chunks[i].len; in iwl_pcie_load_payloads_segments()
416 data = pnvm_data->chunks[i].data; in iwl_pcie_load_payloads_segments()
423 trans->dev); in iwl_pcie_load_payloads_segments()
424 return -ENOMEM; in iwl_pcie_load_payloads_segments()
427 dram_regions->n_regions++; in iwl_pcie_load_payloads_segments()
432 addresses = desc_dram->block; in iwl_pcie_load_payloads_segments()
433 for (i = 0; i < pnvm_data->n_chunks; i++) { in iwl_pcie_load_payloads_segments()
434 addresses->mem_descs[i] = in iwl_pcie_load_payloads_segments()
435 cpu_to_le64(dram_regions->drams[i].physical); in iwl_pcie_load_payloads_segments()
448 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_trans_pcie_ctx_info_v2_load_pnvm()
449 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; in iwl_trans_pcie_ctx_info_v2_load_pnvm()
453 if (trans->pnvm_loaded) in iwl_trans_pcie_ctx_info_v2_load_pnvm()
456 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size)) in iwl_trans_pcie_ctx_info_v2_load_pnvm()
457 return -EBUSY; in iwl_trans_pcie_ctx_info_v2_load_pnvm()
459 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_v2_load_pnvm()
462 if (!pnvm_payloads->n_chunks) { in iwl_trans_pcie_ctx_info_v2_load_pnvm()
464 return -EINVAL; in iwl_trans_pcie_ctx_info_v2_load_pnvm()
473 trans->pnvm_loaded = true; in iwl_trans_pcie_ctx_info_v2_load_pnvm()
477 &dram_regions->drams[0]); in iwl_trans_pcie_ctx_info_v2_load_pnvm()
479 dram_regions->n_regions = 1; in iwl_trans_pcie_ctx_info_v2_load_pnvm()
480 trans->pnvm_loaded = true; in iwl_trans_pcie_ctx_info_v2_load_pnvm()
493 for (i = 0; i < dram_regions->n_regions; i++) in iwl_dram_regions_size()
494 total_size += dram_regions->drams[i].size; in iwl_dram_regions_size()
503 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_pnvm_segments()
504 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data; in iwl_pcie_set_pnvm_segments()
506 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = in iwl_pcie_set_pnvm_segments()
507 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); in iwl_pcie_set_pnvm_segments()
508 prph_sc_ctrl->pnvm_cfg.pnvm_size = in iwl_pcie_set_pnvm_segments()
516 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_contig_pnvm()
518 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr = in iwl_pcie_set_contig_pnvm()
519 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical); in iwl_pcie_set_contig_pnvm()
520 prph_sc_ctrl->pnvm_cfg.pnvm_size = in iwl_pcie_set_contig_pnvm()
521 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size); in iwl_pcie_set_contig_pnvm()
527 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_v2_set_pnvm()
542 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
543 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
547 if (trans->reduce_power_loaded) in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
550 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
553 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size)) in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
554 return -EBUSY; in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
556 if (!payloads->n_chunks) { in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
558 return -EINVAL; in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
567 trans->reduce_power_loaded = true; in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
571 &dram_regions->drams[0]); in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
573 dram_regions->n_regions = 1; in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
574 trans->reduce_power_loaded = true; in iwl_trans_pcie_ctx_info_v2_load_reduce_power()
585 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_reduce_power_segments()
586 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data; in iwl_pcie_set_reduce_power_segments()
588 prph_sc_ctrl->reduce_power_cfg.base_addr = in iwl_pcie_set_reduce_power_segments()
589 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical); in iwl_pcie_set_reduce_power_segments()
590 prph_sc_ctrl->reduce_power_cfg.size = in iwl_pcie_set_reduce_power_segments()
598 &trans_pcie->prph_scratch->ctrl_cfg; in iwl_pcie_set_contig_reduce_power()
600 prph_sc_ctrl->reduce_power_cfg.base_addr = in iwl_pcie_set_contig_reduce_power()
601 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical); in iwl_pcie_set_contig_reduce_power()
602 prph_sc_ctrl->reduce_power_cfg.size = in iwl_pcie_set_contig_reduce_power()
603 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size); in iwl_pcie_set_contig_reduce_power()
610 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_ctx_info_v2_set_reduce_power()