3612 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_lock()
3633 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_tx_unlock()
3653 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_lock()
3664 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_tx_unlock()
3684 	lockdep_assert_held(&ar->htt.tx_lock);  in ath10k_mac_vif_handle_tx_pause()
3729 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3734 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_handle_tx_pause_vdev()
3772 	if (ar->htt.target_version_major < 3 &&  in ath10k_mac_tx_h_get_txmode()
3974 	return (ar->htt.target_version_major >= 3 &&  in ath10k_mac_tx_frm_has_freq()
3975 		ar->htt.target_version_minor >= 4 &&  in ath10k_mac_tx_frm_has_freq()
4010 		else if (ar->htt.target_version_major >= 3)  in ath10k_mac_tx_h_get_txpath()
4024 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_submit()  local
4029 		ret = ath10k_htt_tx(htt, txmode, skb);  in ath10k_mac_tx_submit()
4032 		ret = ath10k_htt_mgmt_tx(htt, skb);  in ath10k_mac_tx_submit()
4302 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4303 	idr_for_each_entry(&ar->htt.pending_tx, msdu, msdu_id) {  in ath10k_mac_txq_unref()
4308 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_txq_unref()
4341 	if (ar->htt.tx_q_state.mode == HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_can_push()
4344 	if (ar->htt.num_pending_tx < ar->htt.tx_q_state.num_push_allowed)  in ath10k_mac_tx_can_push()
4403 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_tx_push_txq()  local
4416 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4417 	ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_tx_push_txq()
4418 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4425 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4426 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4427 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4444 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4445 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_tx_push_txq()
4448 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4449 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4452 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4459 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4460 		ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4462 			ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_tx_push_txq()
4463 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4468 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4470 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_tx_push_txq()
4502 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_tx_push_pending()
4505 	if (ar->htt.num_pending_tx >= (ar->htt.max_num_pending_tx / 2))  in ath10k_mac_tx_push_pending()
4691 	struct ath10k_htt *htt = &ar->htt;  in ath10k_mac_op_tx()  local
4715 		spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4722 		ret = ath10k_htt_tx_inc_pending(htt);  in ath10k_mac_op_tx()
4726 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4731 		ret = ath10k_htt_tx_mgmt_inc_pending(htt, is_mgmt, is_presp);  in ath10k_mac_op_tx()
4735 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4736 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4740 		spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4747 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4748 			ath10k_htt_tx_dec_pending(htt);  in ath10k_mac_op_tx()
4750 				ath10k_htt_tx_mgmt_dec_pending(htt);  in ath10k_mac_op_tx()
4751 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_op_tx()
4765 	if (ar->htt.tx_q_state.mode != HTT_TX_MODE_SWITCH_PUSH)  in ath10k_mac_op_wake_tx_queue()
5882 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
5885 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_add_interface()
6029 	spin_lock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
6031 	spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_remove_interface()
8101 	time_left = wait_event_timeout(ar->htt.empty_tx_wq, ({  in ath10k_mac_wait_tx_complete()
8104 			spin_lock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
8105 			empty = (ar->htt.num_pending_tx == 0);  in ath10k_mac_wait_tx_complete()
8106 			spin_unlock_bh(&ar->htt.tx_lock);  in ath10k_mac_wait_tx_complete()
8135 			ath10k_htt_flush_tx(&ar->htt);  in ath10k_flush()
9390 	if (ar->htt.disable_tx_comp) {  in ath10k_sta_statistics()