46 	ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);  in ravb_modify()
92 		ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);  in ravb_set_rate_gbeth()
95 		ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);  in ravb_set_rate_gbeth()
98 		ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);  in ravb_set_rate_gbeth()
109 		ravb_write(ndev, GECMR_SPEED_100, GECMR);  in ravb_set_rate_rcar()
112 		ravb_write(ndev, GECMR_SPEED_1000, GECMR);  in ravb_set_rate_rcar()
496 	ravb_write(ndev, 0, CSR0);  in ravb_csum_init_gbeth()
507 			ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1);  in ravb_csum_init_gbeth()
510 			ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4,  in ravb_csum_init_gbeth()
515 	ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);  in ravb_csum_init_gbeth()
523 		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);  in ravb_emac_init_gbeth()
526 		ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35);  in ravb_emac_init_gbeth()
532 	ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR);  in ravb_emac_init_gbeth()
535 	ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |  in ravb_emac_init_gbeth()
542 	ravb_write(ndev,  in ravb_emac_init_gbeth()
545 	ravb_write(ndev, (ndev->dev_addr[4] << 8)  | (ndev->dev_addr[5]), MALR);  in ravb_emac_init_gbeth()
548 	ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);  in ravb_emac_init_gbeth()
553 	ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);  in ravb_emac_init_gbeth()
567 	ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR);  in ravb_emac_init_rcar()
570 	ravb_write(ndev, ECMR_ZPF | ECMR_DM |  in ravb_emac_init_rcar()
577 	ravb_write(ndev,  in ravb_emac_init_rcar()
580 	ravb_write(ndev,  in ravb_emac_init_rcar()
584 	ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);  in ravb_emac_init_rcar()
587 	ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);  in ravb_emac_init_rcar()
622 	ravb_write(ndev, 0x60000000, RCR);  in ravb_dmac_init_gbeth()
625 	ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC);  in ravb_dmac_init_gbeth()
628 	ravb_write(ndev, 0x00222200, TGC);  in ravb_dmac_init_gbeth()
630 	ravb_write(ndev, 0, TCCR);  in ravb_dmac_init_gbeth()
633 	ravb_write(ndev, RIC0_FRE0, RIC0);  in ravb_dmac_init_gbeth()
635 	ravb_write(ndev, 0x0, RIC1);  in ravb_dmac_init_gbeth()
637 	ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);  in ravb_dmac_init_gbeth()
639 	ravb_write(ndev, TIC_FTE0, TIC);  in ravb_dmac_init_gbeth()
664 	ravb_write(ndev,  in ravb_dmac_init_rcar()
668 	ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);  in ravb_dmac_init_rcar()
671 	ravb_write(ndev, TCCR_TFEN, TCCR);  in ravb_dmac_init_rcar()
676 		ravb_write(ndev, 0, DIL);  in ravb_dmac_init_rcar()
678 		ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);  in ravb_dmac_init_rcar()
681 	ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);  in ravb_dmac_init_rcar()
683 	ravb_write(ndev, 0, RIC1);  in ravb_dmac_init_rcar()
685 	ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);  in ravb_dmac_init_rcar()
687 	ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);  in ravb_dmac_init_rcar()
1111 	ravb_write(ndev, ecsr, ECSR);	/* clear interrupt */  in ravb_emac_interrupt_unlocked()
1164 	ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);  in ravb_error_interrupt()
1167 		ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),  in ravb_error_interrupt()
1197 				ravb_write(ndev, ric0 & ~BIT(q), RIC0);  in ravb_queue_interrupt()
1198 				ravb_write(ndev, tic & ~BIT(q), TIC);  in ravb_queue_interrupt()
1200 				ravb_write(ndev, BIT(q), RID0);  in ravb_queue_interrupt()
1201 				ravb_write(ndev, BIT(q), TID);  in ravb_queue_interrupt()
1222 		ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);  in ravb_timestamp_interrupt()
1380 	ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);  in ravb_poll()
1386 	ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);  in ravb_poll()
1407 			ravb_write(ndev, mask, RIE0);  in ravb_poll()
1408 			ravb_write(ndev, mask, TIE);  in ravb_poll()
1839 	ravb_write(ndev, priv->gti_tiv, GTI);  in ravb_set_gti()
1950 	ravb_write(ndev, priv->desc_bat_dma, DBAT);  in ravb_open()
2263 		ravb_write(ndev, 0, TROCR);	/* (write clear) */  in ravb_get_stats()
2268 		ravb_write(ndev, 0, CXR41);	/* (write clear) */  in ravb_get_stats()
2270 		ravb_write(ndev, 0, CXR42);	/* (write clear) */  in ravb_get_stats()
2330 	ravb_write(ndev, 0, RIC0);  in ravb_close()
2331 	ravb_write(ndev, 0, RIC2);  in ravb_close()
2332 	ravb_write(ndev, 0, TIC);  in ravb_close()
2511 	ravb_write(ndev, csr0 & ~mask, CSR0);  in ravb_endisable_csum_gbeth()
2514 		ravb_write(ndev, val, reg);  in ravb_endisable_csum_gbeth()
2516 	ravb_write(ndev, csr0, CSR0);  in ravb_endisable_csum_gbeth()
3148 	ravb_write(ndev, 0, RIC0);  in ravb_wol_setup()
3149 	ravb_write(ndev, 0, RIC2);  in ravb_wol_setup()
3150 	ravb_write(ndev, 0, TIC);  in ravb_wol_setup()
3157 	ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);  in ravb_wol_setup()