Lines Matching +full:tdqsck +full:- +full:max
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/devfreq-event.h>
101 * struct dmc_opp_table - Operating level desciption
113 * struct exynos5_dmc - main structure describing DMC device
196 __val = (t_val) << (timing)->bit_beg; \
220 TIMING_FIELD("tW2W-C2C", 14, 14),
221 TIMING_FIELD("tR2R-C2C", 12, 12),
223 TIMING_FIELD("tDQSCK", 4, 7),
243 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_set_event()
244 if (!dmc->counter[i]) in exynos5_counters_set_event()
246 ret = devfreq_event_set_event(dmc->counter[i]); in exynos5_counters_set_event()
257 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_enable_edev()
258 if (!dmc->counter[i]) in exynos5_counters_enable_edev()
260 ret = devfreq_event_enable_edev(dmc->counter[i]); in exynos5_counters_enable_edev()
271 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_disable_edev()
272 if (!dmc->counter[i]) in exynos5_counters_disable_edev()
274 ret = devfreq_event_disable_edev(dmc->counter[i]); in exynos5_counters_disable_edev()
282 * find_target_freq_idx() - Finds requested frequency in local DMC configuration
294 for (i = dmc->opp_count - 1; i >= 0; i--) in find_target_freq_idx()
295 if (dmc->opp[i].freq_hz <= target_rate) in find_target_freq_idx()
298 return -EINVAL; in find_target_freq_idx()
302 * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings
319 ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®); in exynos5_switch_timing_regs()
328 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg); in exynos5_switch_timing_regs()
334 * exynos5_init_freq_table() - Initialized PM OPP framework
343 struct device *dev = dmc->dev; in exynos5_init_freq_table()
354 dmc->opp_count = dev_pm_opp_get_opp_count(dev); in exynos5_init_freq_table()
356 dmc->opp = devm_kmalloc_array(dev, dmc->opp_count, in exynos5_init_freq_table()
358 if (!dmc->opp) in exynos5_init_freq_table()
359 return -ENOMEM; in exynos5_init_freq_table()
361 idx = dmc->opp_count - 1; in exynos5_init_freq_table()
362 for (i = 0, freq = ULONG_MAX; i < dmc->opp_count; i++, freq--) { in exynos5_init_freq_table()
369 dmc->opp[idx - i].freq_hz = freq; in exynos5_init_freq_table()
370 dmc->opp[idx - i].volt_uv = dev_pm_opp_get_voltage(opp); in exynos5_init_freq_table()
379 * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings
382 * Low-level function for changing timings for DRAM memory clocking from
389 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_set_bypass_dram_timings()
391 writel(dmc->bypass_timing_row, in exynos5_set_bypass_dram_timings()
392 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()
393 writel(dmc->bypass_timing_row, in exynos5_set_bypass_dram_timings()
394 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); in exynos5_set_bypass_dram_timings()
395 writel(dmc->bypass_timing_data, in exynos5_set_bypass_dram_timings()
396 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); in exynos5_set_bypass_dram_timings()
397 writel(dmc->bypass_timing_data, in exynos5_set_bypass_dram_timings()
398 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); in exynos5_set_bypass_dram_timings()
399 writel(dmc->bypass_timing_power, in exynos5_set_bypass_dram_timings()
400 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); in exynos5_set_bypass_dram_timings()
401 writel(dmc->bypass_timing_power, in exynos5_set_bypass_dram_timings()
402 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); in exynos5_set_bypass_dram_timings()
406 * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings
410 * Low-level function for changing timings for DRAM memory operating from main
421 for (idx = dmc->opp_count - 1; idx >= 0; idx--) in exynos5_dram_change_timings()
422 if (dmc->opp[idx].freq_hz <= target_rate) in exynos5_dram_change_timings()
426 return -EINVAL; in exynos5_dram_change_timings()
429 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); in exynos5_dram_change_timings()
431 writel(dmc->timing_row[idx], in exynos5_dram_change_timings()
432 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()
433 writel(dmc->timing_row[idx], in exynos5_dram_change_timings()
434 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); in exynos5_dram_change_timings()
435 writel(dmc->timing_data[idx], in exynos5_dram_change_timings()
436 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); in exynos5_dram_change_timings()
437 writel(dmc->timing_data[idx], in exynos5_dram_change_timings()
438 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); in exynos5_dram_change_timings()
439 writel(dmc->timing_power[idx], in exynos5_dram_change_timings()
440 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); in exynos5_dram_change_timings()
441 writel(dmc->timing_power[idx], in exynos5_dram_change_timings()
442 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); in exynos5_dram_change_timings()
448 * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC
462 if (dmc->curr_volt <= target_volt) in exynos5_dmc_align_target_voltage()
465 ret = regulator_set_voltage(dmc->vdd_mif, target_volt, in exynos5_dmc_align_target_voltage()
468 dmc->curr_volt = target_volt; in exynos5_dmc_align_target_voltage()
474 * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC
488 if (dmc->curr_volt >= target_volt) in exynos5_dmc_align_bypass_voltage()
491 ret = regulator_set_voltage(dmc->vdd_mif, target_volt, in exynos5_dmc_align_bypass_voltage()
494 dmc->curr_volt = target_volt; in exynos5_dmc_align_bypass_voltage()
500 * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings
512 return -EINVAL; in exynos5_dmc_align_bypass_dram_timings()
520 * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock
562 * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC
574 * T-period. There is two bank sets for keeping DRAM
600 clk_prepare_enable(dmc->fout_spll); in exynos5_dmc_change_freq_and_volt()
601 clk_prepare_enable(dmc->mout_spll); in exynos5_dmc_change_freq_and_volt()
602 clk_prepare_enable(dmc->mout_mx_mspll_ccore); in exynos5_dmc_change_freq_and_volt()
604 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_mx_mspll_ccore); in exynos5_dmc_change_freq_and_volt()
615 clk_set_rate(dmc->fout_bpll, target_rate); in exynos5_dmc_change_freq_and_volt()
621 ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll); in exynos5_dmc_change_freq_and_volt()
632 clk_disable_unprepare(dmc->mout_mx_mspll_ccore); in exynos5_dmc_change_freq_and_volt()
633 clk_disable_unprepare(dmc->mout_spll); in exynos5_dmc_change_freq_and_volt()
634 clk_disable_unprepare(dmc->fout_spll); in exynos5_dmc_change_freq_and_volt()
640 * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP
661 opp = devfreq_recommended_opp(dmc->dev, freq, flags); in exynos5_dmc_get_volt_freq()
673 * exynos5_dmc_target() - Function responsible for changing frequency of DMC
698 if (target_rate == dmc->curr_rate) in exynos5_dmc_target()
701 mutex_lock(&dmc->lock); in exynos5_dmc_target()
706 mutex_unlock(&dmc->lock); in exynos5_dmc_target()
710 dmc->curr_rate = target_rate; in exynos5_dmc_target()
712 mutex_unlock(&dmc->lock); in exynos5_dmc_target()
717 * exynos5_counters_get() - Gets the performance counters values.
723 * two DMC channels. The 'total_count' is used as a reference and max value.
737 for (i = 0; i < dmc->num_counters; i++) { in exynos5_counters_get()
738 if (!dmc->counter[i]) in exynos5_counters_get()
741 ret = devfreq_event_get_event(dmc->counter[i], &event); in exynos5_counters_get()
757 * exynos5_dmc_start_perf_events() - Setup and start performance event counters
768 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENS_PPC); in exynos5_dmc_start_perf_events()
769 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENS_PPC); in exynos5_dmc_start_perf_events()
772 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENS_PPC); in exynos5_dmc_start_perf_events()
773 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENS_PPC); in exynos5_dmc_start_perf_events()
776 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); in exynos5_dmc_start_perf_events()
777 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); in exynos5_dmc_start_perf_events()
780 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
781 writel(CC_RESET | PPC_COUNTER_RESET, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
785 * will be gathered is calculated as: 0xffffffff - beg_value in exynos5_dmc_start_perf_events()
787 writel(beg_value, dmc->base_drexi0 + DREX_PMCNT2_PPC); in exynos5_dmc_start_perf_events()
788 writel(beg_value, dmc->base_drexi1 + DREX_PMCNT2_PPC); in exynos5_dmc_start_perf_events()
791 writel(PPC_ENABLE, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
792 writel(PPC_ENABLE, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_start_perf_events()
796 * exynos5_dmc_perf_events_calc() - Calculate utilization
821 dmc->load = 70; in exynos5_dmc_perf_events_calc()
822 dmc->total = 100; in exynos5_dmc_perf_events_calc()
828 dmc->load = 35; in exynos5_dmc_perf_events_calc()
829 dmc->total = 100; in exynos5_dmc_perf_events_calc()
832 dev_dbg(dmc->dev, "diff_ts=%llu\n", diff_ts); in exynos5_dmc_perf_events_calc()
836 * exynos5_dmc_perf_events_check() - Checks the status of the counters
850 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_perf_events_check()
851 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_perf_events_check()
854 val = readl(dmc->base_drexi0 + DREX_FLAG_PPC); in exynos5_dmc_perf_events_check()
856 diff_ts = ts - dmc->last_overflow_ts[0]; in exynos5_dmc_perf_events_check()
857 dmc->last_overflow_ts[0] = ts; in exynos5_dmc_perf_events_check()
858 dev_dbg(dmc->dev, "drex0 0xE050 val= 0x%08x\n", val); in exynos5_dmc_perf_events_check()
860 val = readl(dmc->base_drexi1 + DREX_FLAG_PPC); in exynos5_dmc_perf_events_check()
861 diff_ts = ts - dmc->last_overflow_ts[1]; in exynos5_dmc_perf_events_check()
862 dmc->last_overflow_ts[1] = ts; in exynos5_dmc_perf_events_check()
863 dev_dbg(dmc->dev, "drex1 0xE050 val= 0x%08x\n", val); in exynos5_dmc_perf_events_check()
872 * exynos5_dmc_enable_perf_events() - Enable performance events
882 writel(PEREV_CLK_EN, dmc->base_drexi0 + DREX_PPCCLKCON); in exynos5_dmc_enable_perf_events()
883 writel(PEREV_CLK_EN, dmc->base_drexi1 + DREX_PPCCLKCON); in exynos5_dmc_enable_perf_events()
886 writel(READ_TRANSFER_CH0, dmc->base_drexi0 + DREX_PEREV2CONFIG); in exynos5_dmc_enable_perf_events()
887 writel(READ_TRANSFER_CH1, dmc->base_drexi1 + DREX_PEREV2CONFIG); in exynos5_dmc_enable_perf_events()
890 dmc->last_overflow_ts[0] = ts; in exynos5_dmc_enable_perf_events()
891 dmc->last_overflow_ts[1] = ts; in exynos5_dmc_enable_perf_events()
894 dmc->load = 99; in exynos5_dmc_enable_perf_events()
895 dmc->total = 100; in exynos5_dmc_enable_perf_events()
899 * exynos5_dmc_disable_perf_events() - Disable performance events
907 writel(0, dmc->base_drexi0 + DREX_PMNC_PPC); in exynos5_dmc_disable_perf_events()
908 writel(0, dmc->base_drexi1 + DREX_PMNC_PPC); in exynos5_dmc_disable_perf_events()
911 writel(PERF_CNT2, dmc->base_drexi0 + DREX_INTENC_PPC); in exynos5_dmc_disable_perf_events()
912 writel(PERF_CNT2, dmc->base_drexi1 + DREX_INTENC_PPC); in exynos5_dmc_disable_perf_events()
915 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_CNTENC_PPC); in exynos5_dmc_disable_perf_events()
916 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_CNTENC_PPC); in exynos5_dmc_disable_perf_events()
919 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi0 + DREX_FLAG_PPC); in exynos5_dmc_disable_perf_events()
920 writel(PERF_CNT2 | PERF_CCNT, dmc->base_drexi1 + DREX_FLAG_PPC); in exynos5_dmc_disable_perf_events()
924 * exynos5_dmc_get_status() - Read current DMC performance statistics.
939 if (dmc->in_irq_mode) { in exynos5_dmc_get_status()
940 mutex_lock(&dmc->lock); in exynos5_dmc_get_status()
941 stat->current_frequency = dmc->curr_rate; in exynos5_dmc_get_status()
942 mutex_unlock(&dmc->lock); in exynos5_dmc_get_status()
944 stat->busy_time = dmc->load; in exynos5_dmc_get_status()
945 stat->total_time = dmc->total; in exynos5_dmc_get_status()
949 return -EINVAL; in exynos5_dmc_get_status()
952 stat->busy_time = load >> 10; in exynos5_dmc_get_status()
953 stat->total_time = total >> 10; in exynos5_dmc_get_status()
966 * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency
978 mutex_lock(&dmc->lock); in exynos5_dmc_get_cur_freq()
979 *freq = dmc->curr_rate; in exynos5_dmc_get_cur_freq()
980 mutex_unlock(&dmc->lock); in exynos5_dmc_get_cur_freq()
986 * exynos5_dmc_df_profile - Devfreq governor's profile structure
998 * exynos5_dmc_align_init_freq() - Align initial frequency value
1018 aligned_freq = dmc->opp[idx].freq_hz; in exynos5_dmc_align_init_freq()
1020 aligned_freq = dmc->opp[dmc->opp_count - 1].freq_hz; in exynos5_dmc_align_init_freq()
1026 * create_timings_aligned() - Create register values and align with standard
1046 return -EINVAL; in create_timings_aligned()
1052 val = dmc->timings->tRFC / clk_period_ps; in create_timings_aligned()
1053 val += dmc->timings->tRFC % clk_period_ps ? 1 : 0; in create_timings_aligned()
1054 val = max(val, dmc->min_tck->tRFC); in create_timings_aligned()
1058 val = dmc->timings->tRRD / clk_period_ps; in create_timings_aligned()
1059 val += dmc->timings->tRRD % clk_period_ps ? 1 : 0; in create_timings_aligned()
1060 val = max(val, dmc->min_tck->tRRD); in create_timings_aligned()
1064 val = dmc->timings->tRPab / clk_period_ps; in create_timings_aligned()
1065 val += dmc->timings->tRPab % clk_period_ps ? 1 : 0; in create_timings_aligned()
1066 val = max(val, dmc->min_tck->tRPab); in create_timings_aligned()
1070 val = dmc->timings->tRCD / clk_period_ps; in create_timings_aligned()
1071 val += dmc->timings->tRCD % clk_period_ps ? 1 : 0; in create_timings_aligned()
1072 val = max(val, dmc->min_tck->tRCD); in create_timings_aligned()
1076 val = dmc->timings->tRC / clk_period_ps; in create_timings_aligned()
1077 val += dmc->timings->tRC % clk_period_ps ? 1 : 0; in create_timings_aligned()
1078 val = max(val, dmc->min_tck->tRC); in create_timings_aligned()
1082 val = dmc->timings->tRAS / clk_period_ps; in create_timings_aligned()
1083 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; in create_timings_aligned()
1084 val = max(val, dmc->min_tck->tRAS); in create_timings_aligned()
1089 val = dmc->timings->tWTR / clk_period_ps; in create_timings_aligned()
1090 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1091 val = max(val, dmc->min_tck->tWTR); in create_timings_aligned()
1095 val = dmc->timings->tWR / clk_period_ps; in create_timings_aligned()
1096 val += dmc->timings->tWR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1097 val = max(val, dmc->min_tck->tWR); in create_timings_aligned()
1101 val = dmc->timings->tRTP / clk_period_ps; in create_timings_aligned()
1102 val += dmc->timings->tRTP % clk_period_ps ? 1 : 0; in create_timings_aligned()
1103 val = max(val, dmc->min_tck->tRTP); in create_timings_aligned()
1107 val = dmc->timings->tW2W_C2C / clk_period_ps; in create_timings_aligned()
1108 val += dmc->timings->tW2W_C2C % clk_period_ps ? 1 : 0; in create_timings_aligned()
1109 val = max(val, dmc->min_tck->tW2W_C2C); in create_timings_aligned()
1113 val = dmc->timings->tR2R_C2C / clk_period_ps; in create_timings_aligned()
1114 val += dmc->timings->tR2R_C2C % clk_period_ps ? 1 : 0; in create_timings_aligned()
1115 val = max(val, dmc->min_tck->tR2R_C2C); in create_timings_aligned()
1119 val = dmc->timings->tWL / clk_period_ps; in create_timings_aligned()
1120 val += dmc->timings->tWL % clk_period_ps ? 1 : 0; in create_timings_aligned()
1121 val = max(val, dmc->min_tck->tWL); in create_timings_aligned()
1125 val = dmc->timings->tDQSCK / clk_period_ps; in create_timings_aligned()
1126 val += dmc->timings->tDQSCK % clk_period_ps ? 1 : 0; in create_timings_aligned()
1127 val = max(val, dmc->min_tck->tDQSCK); in create_timings_aligned()
1131 val = dmc->timings->tRL / clk_period_ps; in create_timings_aligned()
1132 val += dmc->timings->tRL % clk_period_ps ? 1 : 0; in create_timings_aligned()
1133 val = max(val, dmc->min_tck->tRL); in create_timings_aligned()
1138 val = dmc->timings->tFAW / clk_period_ps; in create_timings_aligned()
1139 val += dmc->timings->tFAW % clk_period_ps ? 1 : 0; in create_timings_aligned()
1140 val = max(val, dmc->min_tck->tFAW); in create_timings_aligned()
1144 val = dmc->timings->tXSR / clk_period_ps; in create_timings_aligned()
1145 val += dmc->timings->tXSR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1146 val = max(val, dmc->min_tck->tXSR); in create_timings_aligned()
1150 val = dmc->timings->tXP / clk_period_ps; in create_timings_aligned()
1151 val += dmc->timings->tXP % clk_period_ps ? 1 : 0; in create_timings_aligned()
1152 val = max(val, dmc->min_tck->tXP); in create_timings_aligned()
1156 val = dmc->timings->tCKE / clk_period_ps; in create_timings_aligned()
1157 val += dmc->timings->tCKE % clk_period_ps ? 1 : 0; in create_timings_aligned()
1158 val = max(val, dmc->min_tck->tCKE); in create_timings_aligned()
1162 val = dmc->timings->tMRD / clk_period_ps; in create_timings_aligned()
1163 val += dmc->timings->tMRD % clk_period_ps ? 1 : 0; in create_timings_aligned()
1164 val = max(val, dmc->min_tck->tMRD); in create_timings_aligned()
1172 * of_get_dram_timings() - helper function for parsing DT settings for DRAM
1180 struct device *dev = dmc->dev; in of_get_dram_timings()
1185 of_parse_phandle(dev->of_node, "device-handle", 0); in of_get_dram_timings()
1187 dev_warn(dev, "could not find 'device-handle' in DT\n"); in of_get_dram_timings()
1188 return -EINVAL; in of_get_dram_timings()
1191 dmc->timing_row = devm_kmalloc_array(dev, TIMING_COUNT, in of_get_dram_timings()
1193 if (!dmc->timing_row) in of_get_dram_timings()
1194 return -ENOMEM; in of_get_dram_timings()
1196 dmc->timing_data = devm_kmalloc_array(dev, TIMING_COUNT, in of_get_dram_timings()
1198 if (!dmc->timing_data) in of_get_dram_timings()
1199 return -ENOMEM; in of_get_dram_timings()
1201 dmc->timing_power = devm_kmalloc_array(dev, TIMING_COUNT, in of_get_dram_timings()
1203 if (!dmc->timing_power) in of_get_dram_timings()
1204 return -ENOMEM; in of_get_dram_timings()
1206 dmc->timings = of_lpddr3_get_ddr_timings(np_ddr, dev, in of_get_dram_timings()
1208 &dmc->timings_arr_size); in of_get_dram_timings()
1209 if (!dmc->timings) { in of_get_dram_timings()
1211 return -EINVAL; in of_get_dram_timings()
1214 dmc->min_tck = of_lpddr3_get_min_tck(np_ddr, dev); in of_get_dram_timings()
1215 if (!dmc->min_tck) { in of_get_dram_timings()
1217 return -EINVAL; in of_get_dram_timings()
1221 for (idx = 0; idx < dmc->opp_count; idx++) { in of_get_dram_timings()
1222 freq_mhz = dmc->opp[idx].freq_hz / 1000000; in of_get_dram_timings()
1225 ret = create_timings_aligned(dmc, &dmc->timing_row[idx], in of_get_dram_timings()
1226 &dmc->timing_data[idx], in of_get_dram_timings()
1227 &dmc->timing_power[idx], in of_get_dram_timings()
1233 dmc->bypass_timing_row = dmc->timing_row[idx - 1]; in of_get_dram_timings()
1234 dmc->bypass_timing_data = dmc->timing_data[idx - 1]; in of_get_dram_timings()
1235 dmc->bypass_timing_power = dmc->timing_power[idx - 1]; in of_get_dram_timings()
1241 * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation.
1250 struct device *dev = dmc->dev; in exynos5_dmc_init_clks()
1255 dmc->fout_spll = devm_clk_get(dev, "fout_spll"); in exynos5_dmc_init_clks()
1256 if (IS_ERR(dmc->fout_spll)) in exynos5_dmc_init_clks()
1257 return PTR_ERR(dmc->fout_spll); in exynos5_dmc_init_clks()
1259 dmc->fout_bpll = devm_clk_get(dev, "fout_bpll"); in exynos5_dmc_init_clks()
1260 if (IS_ERR(dmc->fout_bpll)) in exynos5_dmc_init_clks()
1261 return PTR_ERR(dmc->fout_bpll); in exynos5_dmc_init_clks()
1263 dmc->mout_mclk_cdrex = devm_clk_get(dev, "mout_mclk_cdrex"); in exynos5_dmc_init_clks()
1264 if (IS_ERR(dmc->mout_mclk_cdrex)) in exynos5_dmc_init_clks()
1265 return PTR_ERR(dmc->mout_mclk_cdrex); in exynos5_dmc_init_clks()
1267 dmc->mout_bpll = devm_clk_get(dev, "mout_bpll"); in exynos5_dmc_init_clks()
1268 if (IS_ERR(dmc->mout_bpll)) in exynos5_dmc_init_clks()
1269 return PTR_ERR(dmc->mout_bpll); in exynos5_dmc_init_clks()
1271 dmc->mout_mx_mspll_ccore = devm_clk_get(dev, "mout_mx_mspll_ccore"); in exynos5_dmc_init_clks()
1272 if (IS_ERR(dmc->mout_mx_mspll_ccore)) in exynos5_dmc_init_clks()
1273 return PTR_ERR(dmc->mout_mx_mspll_ccore); in exynos5_dmc_init_clks()
1275 dmc->mout_spll = devm_clk_get(dev, "ff_dout_spll2"); in exynos5_dmc_init_clks()
1276 if (IS_ERR(dmc->mout_spll)) { in exynos5_dmc_init_clks()
1277 dmc->mout_spll = devm_clk_get(dev, "mout_sclk_spll"); in exynos5_dmc_init_clks()
1278 if (IS_ERR(dmc->mout_spll)) in exynos5_dmc_init_clks()
1279 return PTR_ERR(dmc->mout_spll); in exynos5_dmc_init_clks()
1285 dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex); in exynos5_dmc_init_clks()
1286 dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); in exynos5_dmc_init_clks()
1287 exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; in exynos5_dmc_init_clks()
1289 ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate, in exynos5_dmc_init_clks()
1294 dmc->curr_volt = target_volt; in exynos5_dmc_init_clks()
1296 ret = clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); in exynos5_dmc_init_clks()
1300 clk_prepare_enable(dmc->fout_bpll); in exynos5_dmc_init_clks()
1301 clk_prepare_enable(dmc->mout_bpll); in exynos5_dmc_init_clks()
1307 regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, &tmp); in exynos5_dmc_init_clks()
1309 regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CLKM_SRC, tmp); in exynos5_dmc_init_clks()
1315 * exynos5_performance_counters_init() - Initializes performance DMC's counters
1325 struct device *dev = dmc->dev; in exynos5_performance_counters_init()
1328 dmc->num_counters = devfreq_event_get_edev_count(dev, "devfreq-events"); in exynos5_performance_counters_init()
1329 if (dmc->num_counters < 0) { in exynos5_performance_counters_init()
1330 dev_err(dev, "could not get devfreq-event counters\n"); in exynos5_performance_counters_init()
1331 return dmc->num_counters; in exynos5_performance_counters_init()
1334 dmc->counter = devm_kcalloc(dev, dmc->num_counters, in exynos5_performance_counters_init()
1335 sizeof(*dmc->counter), GFP_KERNEL); in exynos5_performance_counters_init()
1336 if (!dmc->counter) in exynos5_performance_counters_init()
1337 return -ENOMEM; in exynos5_performance_counters_init()
1339 for (i = 0; i < dmc->num_counters; i++) { in exynos5_performance_counters_init()
1340 dmc->counter[i] = in exynos5_performance_counters_init()
1341 devfreq_event_get_edev_by_phandle(dev, "devfreq-events", i); in exynos5_performance_counters_init()
1342 if (IS_ERR_OR_NULL(dmc->counter[i])) in exynos5_performance_counters_init()
1343 return -EPROBE_DEFER; in exynos5_performance_counters_init()
1363 * exynos5_dmc_set_pause_on_switching() - Controls a pause feature in DMC
1376 ret = regmap_read(dmc->clk_regmap, CDREX_PAUSE, &val); in exynos5_dmc_set_pause_on_switching()
1381 regmap_write(dmc->clk_regmap, CDREX_PAUSE, val); in exynos5_dmc_set_pause_on_switching()
1391 mutex_lock(&dmc->df->lock); in dmc_irq_thread()
1393 res = update_devfreq(dmc->df); in dmc_irq_thread()
1394 mutex_unlock(&dmc->df->lock); in dmc_irq_thread()
1397 dev_warn(dmc->dev, "devfreq failed with %d\n", res); in dmc_irq_thread()
1403 * exynos5_dmc_probe() - Probe function for the DMC driver
1415 struct device *dev = &pdev->dev; in exynos5_dmc_probe()
1416 struct device_node *np = dev->of_node; in exynos5_dmc_probe()
1422 return -ENOMEM; in exynos5_dmc_probe()
1424 mutex_init(&dmc->lock); in exynos5_dmc_probe()
1426 dmc->dev = dev; in exynos5_dmc_probe()
1429 dmc->base_drexi0 = devm_platform_ioremap_resource(pdev, 0); in exynos5_dmc_probe()
1430 if (IS_ERR(dmc->base_drexi0)) in exynos5_dmc_probe()
1431 return PTR_ERR(dmc->base_drexi0); in exynos5_dmc_probe()
1433 dmc->base_drexi1 = devm_platform_ioremap_resource(pdev, 1); in exynos5_dmc_probe()
1434 if (IS_ERR(dmc->base_drexi1)) in exynos5_dmc_probe()
1435 return PTR_ERR(dmc->base_drexi1); in exynos5_dmc_probe()
1437 dmc->clk_regmap = syscon_regmap_lookup_by_phandle(np, in exynos5_dmc_probe()
1438 "samsung,syscon-clk"); in exynos5_dmc_probe()
1439 if (IS_ERR(dmc->clk_regmap)) in exynos5_dmc_probe()
1440 return PTR_ERR(dmc->clk_regmap); in exynos5_dmc_probe()
1448 dmc->vdd_mif = devm_regulator_get(dev, "vdd"); in exynos5_dmc_probe()
1449 if (IS_ERR(dmc->vdd_mif)) { in exynos5_dmc_probe()
1450 ret = PTR_ERR(dmc->vdd_mif); in exynos5_dmc_probe()
1494 dmc->gov_data.upthreshold = 55; in exynos5_dmc_probe()
1495 dmc->gov_data.downdifferential = 5; in exynos5_dmc_probe()
1499 dmc->in_irq_mode = 1; in exynos5_dmc_probe()
1511 dmc->gov_data.upthreshold = 10; in exynos5_dmc_probe()
1512 dmc->gov_data.downdifferential = 5; in exynos5_dmc_probe()
1517 dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, in exynos5_dmc_probe()
1519 &dmc->gov_data); in exynos5_dmc_probe()
1521 if (IS_ERR(dmc->df)) { in exynos5_dmc_probe()
1522 ret = PTR_ERR(dmc->df); in exynos5_dmc_probe()
1526 if (dmc->in_irq_mode) in exynos5_dmc_probe()
1529 dev_info(dev, "DMC initialized, in irq mode: %d\n", dmc->in_irq_mode); in exynos5_dmc_probe()
1534 if (dmc->in_irq_mode) in exynos5_dmc_probe()
1539 clk_disable_unprepare(dmc->mout_bpll); in exynos5_dmc_probe()
1540 clk_disable_unprepare(dmc->fout_bpll); in exynos5_dmc_probe()
1546 * exynos5_dmc_remove() - Remove function for the platform device
1555 struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); in exynos5_dmc_remove()
1557 if (dmc->in_irq_mode) in exynos5_dmc_remove()
1562 clk_disable_unprepare(dmc->mout_bpll); in exynos5_dmc_remove()
1563 clk_disable_unprepare(dmc->fout_bpll); in exynos5_dmc_remove()
1567 { .compatible = "samsung,exynos5422-dmc", },
1576 .name = "exynos5-dmc",