23 #define OV4689_REG_CTRL_MODE		CCI_REG8(0x0100)
24 #define OV4689_MODE_SW_STANDBY		0x0
25 #define OV4689_MODE_STREAMING		BIT(0)
27 #define OV4689_REG_CHIP_ID		CCI_REG16(0x300a)
28 #define CHIP_ID				0x004688
30 #define OV4689_REG_EXPOSURE		CCI_REG24(0x3500)
34 #define OV4689_REG_GAIN			CCI_REG16(0x3508)
36 #define OV4689_GAIN_DEFAULT		0x80
38 #define OV4689_REG_DIG_GAIN		CCI_REG16(0x352a)
40 #define OV4689_DIG_GAIN_MAX		0x7fff
42 #define OV4689_DIG_GAIN_DEFAULT		0x800
44 #define OV4689_REG_H_CROP_START		CCI_REG16(0x3800)
45 #define OV4689_REG_V_CROP_START		CCI_REG16(0x3802)
46 #define OV4689_REG_H_CROP_END		CCI_REG16(0x3804)
47 #define OV4689_REG_V_CROP_END		CCI_REG16(0x3806)
48 #define OV4689_REG_H_OUTPUT_SIZE	CCI_REG16(0x3808)
49 #define OV4689_REG_V_OUTPUT_SIZE	CCI_REG16(0x380a)
51 #define OV4689_REG_HTS			CCI_REG16(0x380c)
53 #define OV4689_HTS_MAX			0x7fff
55 #define OV4689_REG_VTS			CCI_REG16(0x380e)
56 #define OV4689_VTS_MAX			0x7fff
58 #define OV4689_REG_H_WIN_OFF		CCI_REG16(0x3810)
59 #define OV4689_REG_V_WIN_OFF		CCI_REG16(0x3812)
61 #define OV4689_REG_TIMING_FORMAT1	CCI_REG8(0x3820) /* Vertical */
62 #define OV4689_REG_TIMING_FORMAT2	CCI_REG8(0x3821) /* Horizontal */
69 #define OV4689_REG_ANCHOR_LEFT_START	CCI_REG16(0x4020)
71 #define OV4689_REG_ANCHOR_LEFT_END	CCI_REG16(0x4022)
73 #define OV4689_REG_ANCHOR_RIGHT_START	CCI_REG16(0x4024)
75 #define OV4689_REG_ANCHOR_RIGHT_END	CCI_REG16(0x4026)
78 #define OV4689_REG_VFIFO_CTRL_01	CCI_REG8(0x4601)
80 #define OV4689_REG_WB_GAIN_RED		CCI_REG16(0x500c)
81 #define OV4689_REG_WB_GAIN_BLUE		CCI_REG16(0x5010)
83 #define OV4689_WB_GAIN_MAX		0xfff
85 #define OV4689_WB_GAIN_DEFAULT		0x400
87 #define OV4689_REG_TEST_PATTERN		CCI_REG8(0x5040)
88 #define OV4689_TEST_PATTERN_ENABLE	0x80
89 #define OV4689_TEST_PATTERN_DISABLE	0x0
106 	OV4689_MODE_2688_1520 = 0,
160 	{ CCI_REG8(0x0103), 0x01 }, /* SC_CTRL0103 software_reset = 1 */
161 	{ CCI_REG8(0x3000), 0x20 }, /* SC_CMMN_PAD_OEN0 FSIN_output_enable = 1 */
162 	{ CCI_REG8(0x3021), 0x03 }, /*
163 				     * SC_CMMN_MISC_CTRL fst_stby_ctr = 0,
164 				     * sleep_no_latch_enable = 0
168 	{ CCI_REG8(0x3503), 0x04 }, /* AEC_MANUAL gain_input_as_sensor_gain_format = 1 */
171 	{ CCI_REG8(0x3603), 0x40 },
172 	{ CCI_REG8(0x3604), 0x02 },
173 	{ CCI_REG8(0x3609), 0x12 },
174 	{ CCI_REG8(0x360c), 0x08 },
175 	{ CCI_REG8(0x360f), 0xe5 },
176 	{ CCI_REG8(0x3608), 0x8f },
177 	{ CCI_REG8(0x3611), 0x00 },
178 	{ CCI_REG8(0x3613), 0xf7 },
179 	{ CCI_REG8(0x3616), 0x58 },
180 	{ CCI_REG8(0x3619), 0x99 },
181 	{ CCI_REG8(0x361b), 0x60 },
182 	{ CCI_REG8(0x361e), 0x79 },
183 	{ CCI_REG8(0x3634), 0x10 },
184 	{ CCI_REG8(0x3635), 0x10 },
185 	{ CCI_REG8(0x3636), 0x15 },
186 	{ CCI_REG8(0x3646), 0x86 },
187 	{ CCI_REG8(0x364a), 0x0b },
190 	{ CCI_REG8(0x3700), 0x17 },
191 	{ CCI_REG8(0x3701), 0x22 },
192 	{ CCI_REG8(0x3703), 0x10 },
193 	{ CCI_REG8(0x370a), 0x37 },
194 	{ CCI_REG8(0x3706), 0x63 },
195 	{ CCI_REG8(0x3709), 0x3c },
196 	{ CCI_REG8(0x370c), 0x30 },
197 	{ CCI_REG8(0x3710), 0x24 },
198 	{ CCI_REG8(0x3720), 0x28 },
199 	{ CCI_REG8(0x3729), 0x7b },
200 	{ CCI_REG8(0x372b), 0xbd },
201 	{ CCI_REG8(0x372c), 0xbc },
202 	{ CCI_REG8(0x372e), 0x52 },
203 	{ CCI_REG8(0x373c), 0x0e },
204 	{ CCI_REG8(0x373e), 0x33 },
205 	{ CCI_REG8(0x3743), 0x10 },
206 	{ CCI_REG8(0x3744), 0x88 },
207 	{ CCI_REG8(0x3745), 0xc0 },
208 	{ CCI_REG8(0x374c), 0x00 },
209 	{ CCI_REG8(0x374e), 0x23 },
210 	{ CCI_REG8(0x3751), 0x7b },
211 	{ CCI_REG8(0x3753), 0xbd },
212 	{ CCI_REG8(0x3754), 0xbc },
213 	{ CCI_REG8(0x3756), 0x52 },
214 	{ CCI_REG8(0x376b), 0x20 },
215 	{ CCI_REG8(0x3774), 0x51 },
216 	{ CCI_REG8(0x3776), 0xbd },
217 	{ CCI_REG8(0x3777), 0xbd },
218 	{ CCI_REG8(0x3781), 0x18 },
219 	{ CCI_REG8(0x3783), 0x25 },
220 	{ CCI_REG8(0x3798), 0x1b },
223 	{ CCI_REG8(0x3819), 0x01 }, /* VSYNC_END_L vsync_end_point[7:0] = 0x01 */
226 	{ CCI_REG8(0x3d85), 0x36 }, /* OTP_REG85 OTP_power_up_load_setting_enable = 1,
230 	{ CCI_REG8(0x3d8c), 0x71 }, /* OTP_SETTING_STT_ADDRESS_H */
231 	{ CCI_REG8(0x3d8d), 0xcb }, /* OTP_SETTING_STT_ADDRESS_L */
234 	{ CCI_REG8(0x4001), 0x40 }, /* DEBUG_MODE */
235 	{ CCI_REG8(0x401b), 0x00 }, /* DEBUG_MODE */
236 	{ CCI_REG8(0x401d), 0x00 }, /* DEBUG_MODE */
237 	{ CCI_REG8(0x401f), 0x00 }, /* DEBUG_MODE */
240 	{ CCI_REG8(0x4500), 0x6c }, /* ADC_SYNC_CTRL */
241 	{ CCI_REG8(0x4503), 0x01 }, /* ADC_SYNC_CTRL */
244 	{ CCI_REG8(0x4d00), 0x04 }, /* TPM_CTRL_00 tmp_slope[15:8] = 0x04 */
245 	{ CCI_REG8(0x4d01), 0x42 }, /* TPM_CTRL_01 tmp_slope[7:0] = 0x42 */
246 	{ CCI_REG8(0x4d02), 0xd1 }, /* TPM_CTRL_02 tpm_offset[31:24] = 0xd1 */
247 	{ CCI_REG8(0x4d03), 0x93 }, /* TPM_CTRL_03 tpm_offset[23:16] = 0x93 */
248 	{ CCI_REG8(0x4d04), 0xf5 }, /* TPM_CTRL_04 tpm_offset[15:8]  = 0xf5 */
249 	{ CCI_REG8(0x4d05), 0xc1 }, /* TPM_CTRL_05 tpm_offset[7:0]   = 0xc1 */
252 	{ CCI_REG8(0x5050), 0x0c }, /* DEBUG_MODE */
255 	{ CCI_REG8(0x5501), 0x10 }, /* OTP_DPC_START_L otp_start_address[7:0] = 0x10 */
256 	{ CCI_REG8(0x5503), 0x0f }, /* OTP_DPC_END_L otp_end_address[7:0] = 0x0f */
290 		.logical_min = 0,
292 		.offset = 0,
294 		.physical_min = 0,
342 	return 0;  in ov4689_set_fmt()
349 	if (code->index != 0)  in ov4689_enum_mbus_code()
353 	return 0;  in ov4689_enum_mbus_code()
371 	return 0;  in ov4689_enum_frame_sizes()
396 		sel->r.top = 0;  in ov4689_get_selection()
397 		sel->r.left = 0;  in ov4689_get_selection()
400 		return 0;  in ov4689_get_selection()
409 		return 0;  in ov4689_get_selection()
419 	int ret = 0;  in ov4689_setup_timings()
440 	int ret = 0;  in ov4689_setup_blc_anchors()
455 	int ret = 0;  in ov4689_s_stream()
461 		if (ret < 0)  in ov4689_s_stream()
525 	if (ret < 0) {  in ov4689_power_on()
534 	if (ret < 0) {  in ov4689_power_on()
539 	gpiod_set_value_cansleep(ov4689->reset_gpio, 0);  in ov4689_power_on()
541 	gpiod_set_value_cansleep(ov4689->pwdn_gpio, 0);  in ov4689_power_on()
547 	return 0;  in ov4689_power_on()
565 	return 0;  in ov4689_power_off()
572 		v4l2_subdev_state_get_format(sd_state, 0);  in ov4689_init_state()
576 	return 0;  in ov4689_init_state()
613 	for (n = 0; n < ARRAY_SIZE(ov4689_gain_ranges); n++) {  in ov4689_map_gain()
630 	return 0;  in ov4689_map_gain()
639 	int sensor_gain = 0;  in ov4689_set_ctrl()
641 	int ret = 0;  in ov4689_set_ctrl()
656 		return 0;  in ov4689_set_ctrl()
682 				ctrl->val ? OV4689_TIMING_FLIP_BOTH : 0, &ret);  in ov4689_set_ctrl()
687 				ctrl->val ? 0 : OV4689_TIMING_FLIP_BOTH, &ret);  in ov4689_set_ctrl()
699 		dev_warn(dev, "%s Unhandled id:0x%x, val:0x%x\n",  in ov4689_set_ctrl()
732 	ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0,  in ov4689_initialize_controls()
737 	v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0,  in ov4689_initialize_controls()
758 			  ov4689_gain_ranges[0].logical_min,  in ov4689_initialize_controls()
766 				     0, 0, ov4689_test_pattern_menu);  in ov4689_initialize_controls()
768 	v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);  in ov4689_initialize_controls()
769 	v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);  in ov4689_initialize_controls()
800 	return 0;  in ov4689_initialize_controls()
812 	u64 id = 0;  in ov4689_check_sensor_id()
829 	return 0;  in ov4689_check_sensor_id()
836 	for (i = 0; i < ARRAY_SIZE(ov4689_supply_names); i++)  in ov4689_configure_regulators()
849 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {  in ov4689_check_link_frequency()
850 		for (j = 0; j < ep->nr_of_link_frequencies; j++)  in ov4689_check_link_frequency()
855 	return 0;  in ov4689_check_link_frequency()
980 	if (ret < 0)  in ov4689_probe()
1005 	return 0;  in ov4689_probe()