Lines Matching +full:inter +full:- +full:processor
1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
37 will be discovered and possibly managed at probe-time.
54 processer can write data in a channel, and set co-responding register
55 to raise interrupt to notice another processor, and it is allowed to
101 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
118 This driver provides support for inter-processor communication
119 between CPU cores and MCU processor on Some Rockchip SOCs.
207 module will be called mailbox-mpfs.
212 tristate "Microchip Inter-processor Communication (IPC) SBI driver"
217 Inter-process communication (IPC) controller.
220 module will be called mailbox-mchp-ipc-sbi.
229 providing an interface for invoking the inter-process communication
230 signals from the application processor to other masters.
242 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
245 An implementation of the APM X-Gene Interprocessor Communication
246 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
247 It is used to send short messages between ARM64-bit cores and
249 want to use the APM X-Gene SLIMpro IPCM support.
275 with hardware for Inter-Processor Communication Controller (IPCC)
313 processor to Video Companion Processor Unit.
324 registers to kick the other processor or enquire status.
347 Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
355 Qualcomm Technologies, Inc. Inter-Processor Communication Controller
362 tristate "T-head TH1520 Mailbox"
365 Mailbox driver implementation for the Thead TH-1520 platform. Enables
388 processor and coprocessor that handles various power management task
392 tristate "RISC-V SBI Message Proxy (MPXY) Mailbox"
396 Mailbox driver implementation for RISC-V SBI Message Proxy (MPXY)
398 remote processor through the SBI implementation (M-mode firmware
399 or HS-mode hypervisor). Say Y here, unless you are sure you do not