Lines Matching +full:system +full:- +full:on +full:- +full:a +full:- +full:chip
1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
6 depends on (OF_IRQ || ACPI_GENERIC_GSI)
10 depends on OF
16 depends on PM
21 depends on ARM_GIC
27 depends on PCI
53 depends on ARM_GIC_V3_ITS
54 depends on FSL_MC_BUS
70 depends on ARM_VIC
72 The maximum number of VICs available in the system, for
88 depends on PCI
95 depends on OF
96 depends on HAS_IOMEM
119 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
120 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST
122 depends on ARM_GIC
128 Enable support for the Broadcom BCM2712 MSI-X target peripheral
129 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
141 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
142 depends on ARCH_BRCMSTB || BMIPS_GENERIC
149 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
150 depends on ARCH_BRCMSTB || BMIPS_GENERIC
157 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
199 depends on MCHP_LAN966X_PCI || COMPILE_TEST
204 This controller is present on the Microchip LAN966x PCI device and
207 To compile this driver as a module, choose M here: the module
208 will be called irq-lan966x-oic.
222 depends on ARCH_CLPS711X
249 bool "J-Core integrated AIC" if COMPILE_TEST
250 depends on OF
253 Support for the J-Core integrated AIC.
264 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
267 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
272 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
298 depends on MFD_SL28CPLD=y || COMPILE_TEST
302 found on the Kontron sl28 CPLD.
309 Enables SysCfg Controlled IRQs on STi based platforms.
329 tristate "TS-4800 IRQ controller"
331 depends on HAS_IOMEM
332 depends on SOC_IMX51 || COMPILE_TEST
334 Support for the TS-4800 FPGA IRQ controller
343 depends on VERSATILE_FPGA_IRQ
352 depends on OF_ADDRESS
356 This is used as a primary controller with MicroBlaze and can also
357 be used as a secondary chained controller on other platforms.
362 Support for a CROSSBAR ip that precedes the main interrupt controller.
364 a free irq and configures the IP. Thus the peripheral interrupts are
369 depends on ARCH_KEYSTONE
383 depends on MACH_INGENIC
389 depends on MIPS || COMPILE_TEST
439 depends on PCI_MSI
447 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST
461 depends on ARCH_QCOM && ACPI
469 depends on ARCH_UNIPHIER || COMPILE_TEST
477 depends on ARCH_MESON || COMPILE_TEST
485 depends on MIPS && (GOLDFISH || COMPILE_TEST)
494 depends on ARCH_QCOM
502 depends on ARCH_QCOM
503 depends on MAILBOX
511 depends on CSKY
513 Say yes here to enable C-SKY SMP interrupt controller driver used
514 for C-SKY SMP system.
519 bool "C-SKY APB Interrupt Controller"
520 depends on CSKY
522 Say yes here to enable C-SKY APB interrupt controller driver used
523 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
528 depends on ARCH_MXC || COMPILE_TEST
543 depends on OF && HAS_IOMEM
544 depends on ARCH_MXC || COMPILE_TEST
551 Provide a driver for the i.MX Messaging Unit block used as a
552 CPU-to-CPU MSI controller. This requires a specially crafted DT
558 bool "Loongson-1 Interrupt Controller"
559 depends on MACH_LOONGSON32
564 Support for the Loongson-1 platform Interrupt Controller.
568 depends on TI_SCI_PROTOCOL
569 depends on ARCH_K3 || COMPILE_TEST
573 over TI System Control Interface available on some new TI's SoCs.
575 TI System Controller, say Y here. Otherwise, say N.
579 depends on TI_SCI_PROTOCOL
580 depends on ARCH_K3 || (COMPILE_TEST && ARM64)
585 over TI System Control Interface available on some new TI's SoCs.
587 TI System Controller, say Y here. Otherwise, say N.
591 depends on TI_PRUSS
595 This enables support for the PRU-ICSS Local Interrupt Controller
596 present within a PRU-ICSS subsystem present on various TI SoCs.
602 depends on RISCV
607 depends on RISCV
612 depends on RISCV_APLIC
618 depends on RISCV
626 depends on RISCV
632 depends on ARCH_STARFIVE || COMPILE_TEST
636 This enables support for the INTC chip found in StarFive JH8100
642 bool "RISC-V ACLINT S-mode IPI Interrupt Controller"
643 depends on RISCV
644 depends on SMP
648 This enables support for variants of the RISC-V ACLINT-SSWI device.
650 - T-HEAD, with compatible "thead,c900-aclint-sswi"
651 - MIPS P8700, with compatible "mips,p8700-aclint-sswi"
662 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
680 irq chip hierarchy on LoongArch platforms please read the document
681 Documentation/arch/loongarch/irq-chip-model.rst.
685 depends on MACH_LOONGSON64
694 depends on LOONGARCH
695 depends on MACH_LOONGSON64
704 depends on MACH_LOONGSON64 && MIPS
709 Support for the Loongson-3 HyperTransport PIC Controller.
713 depends on MACH_LOONGSON64
721 depends on MACH_LOONGSON64
730 depends on MACH_LOONGSON64
731 depends on PCI
741 depends on LOONGARCH
742 depends on MACH_LOONGSON64
750 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
759 depends on ARCH_WPCM450
770 depends on ARM64
771 depends on ARCH_APPLE || COMPILE_TEST
774 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
779 depends on ARCH_AT91 || COMPILE_TEST
787 depends on ARCH_SOPHGO || COMPILE_TEST
788 depends on PCI
794 This on-chip interrupt controller enables MSI sources to be
795 routed to the primary PLIC controller on SoC.
802 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
803 chained controller, routing all interrupt source in P-Chip to
804 the primary controller on C-Chip.