Lines Matching +full:sp7021 +full:- +full:intc

1 # SPDX-License-Identifier: GPL-2.0-only
131 	tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
140 	  Enable support for the Broadcom BCM2712 MSI-X target peripheral
141 	  (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
153 	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
161 	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
220 	  will be called irq-lan966x-oic.
261 	bool "J-Core integrated AIC" if COMPILE_TEST
265 	  Support for the J-Core integrated AIC.
272 	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
276 	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
279 	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
284 	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
341 	tristate "TS-4800 IRQ controller"
346 	  Support for the TS-4800 FPGA IRQ controller
525 	  Say yes here to enable C-SKY SMP interrupt controller driver used
526 	  for C-SKY SMP system.
531 	bool "C-SKY APB Interrupt Controller"
534 	  Say yes here to enable C-SKY APB interrupt controller driver used
535 	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
564 	  CPU-to-CPU MSI controller. This requires a specially crafted DT
570 	bool "Loongson-1 Interrupt Controller"
576 	  Support for the Loongson-1 platform Interrupt Controller.
607 	  This enables support for the PRU-ICSS Local Interrupt Controller
608 	  present within a PRU-ICSS subsystem present on various TI SoCs.
609 	  The PRUSS INTC enables various interrupts to be routed to multiple
648 	  This enables support for the INTC chip found in StarFive JH8100
654 	bool "RISC-V ACLINT S-mode IPI Interrupt Controller"
660 	  This enables support for variants of the RISC-V ACLINT-SSWI device.
662 	  - T-HEAD, with compatible "thead,c900-aclint-sswi"
663 	  - MIPS P8700, with compatible "mips,p8700-aclint-sswi"
693 	  Documentation/arch/loongarch/irq-chip-model.rst.
721 	  Support for the Loongson-3 HyperTransport PIC Controller.
806 	  This on-chip interrupt controller enables MSI sources to be
810 	bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
813 	  Support for the Sunplus SP7021 Interrupt Controller IP core.
814 	  SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
815 	  chained controller, routing all interrupt source in P-Chip to
816 	  the primary controller on C-Chip.