Lines Matching +full:lpc +full:- +full:interrupts

1 # SPDX-License-Identifier: GPL-2.0-only
119 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
177 maps the internal interrupts sources to PCIe interrupt.
180 will be called irq-lan966x-oic.
221 bool "J-Core integrated AIC" if COMPILE_TEST
225 Support for the J-Core integrated AIC.
236 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
239 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
244 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
251 to 8 external interrupts with configurable sense select.
301 tristate "TS-4800 IRQ controller"
306 Support for the TS-4800 FPGA IRQ controller
336 a free irq and configures the IP. Thus the peripheral interrupts are
365 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
416 tristate "STM32MP extended interrupts and event controller"
422 Support STM32MP EXTI (extended interrupts and event) controller.
483 Say yes here to enable C-SKY SMP interrupt controller driver used
484 for C-SKY SMP system.
489 bool "C-SKY APB Interrupt Controller"
492 Say yes here to enable C-SKY APB interrupt controller driver used
493 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
522 CPU-to-CPU MSI controller. This requires a specially crafted DT
528 bool "Loongson-1 Interrupt Controller"
534 Support for the Loongson-1 platform Interrupt Controller.
563 This enables support for the PRU-ICSS Local Interrupt Controller
564 present within a PRU-ICSS subsystem present on various TI SoCs.
565 The PRUSS INTC enables various interrupts to be routed to multiple
616 bool "THEAD C9XX ACLINT S-mode IPI Interrupt Controller"
622 This enables support for T-HEAD specific ACLINT SSWI device
648 Documentation/arch/loongarch/irq-chip-model.rst.
676 Support for the Loongson-3 HyperTransport PIC Controller.
707 bool "Loongson PCH LPC Controller"
713 Support for the Loongson PCH LPC Controller.
757 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
758 chained controller, routing all interrupt source in P-Chip to
759 the primary controller on C-Chip.