Lines Matching +full:lpc +full:- +full:interrupts

1 # SPDX-License-Identifier: GPL-2.0-only
119 	tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
127 	tristate "Broadcom STB 7120-style L2 interrupt controller driver"
177 	  maps the internal interrupts sources to PCIe interrupt.
180 	  will be called irq-lan966x-oic.
221 	bool "J-Core integrated AIC" if COMPILE_TEST
225 	  Support for the J-Core integrated AIC.
236 	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
239 	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
244 	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
251 	  to 8 external interrupts with configurable sense select.
294 	tristate "TS-4800 IRQ controller"
299 	  Support for the TS-4800 FPGA IRQ controller
329 	  a free irq and configures the IP. Thus the peripheral interrupts are
357 	  Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
408 	tristate "STM32MP extended interrupts and event controller"
414 	  Support STM32MP EXTI (extended interrupts and event) controller.
475 	  Say yes here to enable C-SKY SMP interrupt controller driver used
476 	  for C-SKY SMP system.
481 	bool "C-SKY APB Interrupt Controller"
484 	  Say yes here to enable C-SKY APB interrupt controller driver used
485 	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
514 	  CPU-to-CPU MSI controller. This requires a specially crafted DT
520 	bool "Loongson-1 Interrupt Controller"
526 	  Support for the Loongson-1 platform Interrupt Controller.
555 	  This enables support for the PRU-ICSS Local Interrupt Controller
556 	  present within a PRU-ICSS subsystem present on various TI SoCs.
557 	  The PRUSS INTC enables various interrupts to be routed to multiple
628 	  Documentation/arch/loongarch/irq-chip-model.rst.
656 	  Support for the Loongson-3 HyperTransport PIC Controller.
687 	bool "Loongson PCH LPC Controller"
693 	  Support for the Loongson PCH LPC Controller.
737 	  SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
738 	  chained controller, routing all interrupt source in P-Chip to
739 	  the primary controller on C-Chip.