Lines Matching +full:chip +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "IRQ chip support"
11 select IRQ_DOMAIN_HIERARCHY
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
17 select ARM_GIC
28 select ARM_GIC
29 select IRQ_MSI_LIB
30 select PCI_MSI
31 select IRQ_MSI_IOMMU
38 select IRQ_DOMAIN_HIERARCHY
39 select PARTITION_PERCPU
40 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
41 select HAVE_ARM_SMCCC_DISCOVERY
42 select IRQ_MSI_IOMMU
49 select GENERIC_MSI_IRQ
50 select IRQ_MSI_LIB
51 select ARM_GIC_ITS_PARENT
53 select IRQ_MSI_IOMMU
63 select IRQ_DOMAIN_HIERARCHY
64 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
65 select GENERIC_MSI_IRQ
66 select IRQ_MSI_LIB
67 select ARM_GIC_ITS_PARENT
71 select IRQ_DOMAIN_HIERARCHY
72 select GENERIC_IRQ_CHIP
76 select IRQ_DOMAIN
89 select GENERIC_MSI_IRQ
93 select GENERIC_IRQ_CHIP
94 select PCI_MSI if PCI
95 select IRQ_MSI_LIB if PCI
96 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
101 select PCI_MSI
102 select IRQ_MSI_LIB
103 select GENERIC_IRQ_CHIP
109 select GENERIC_IRQ_CHIP
110 select IRQ_DOMAIN
116 select GENERIC_IRQ_CHIP
117 select IRQ_DOMAIN
118 select SPARSE_IRQ
122 select GENERIC_IRQ_CHIP
123 select IRQ_DOMAIN
124 select SPARSE_IRQ
128 select IRQ_DOMAIN
131 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support"
135 select GENERIC_IRQ_CHIP
136 select IRQ_DOMAIN_HIERARCHY
137 select GENERIC_MSI_IRQ
138 select IRQ_MSI_LIB
140 Enable support for the Broadcom BCM2712 MSI-X target peripheral
141 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on
148 select GENERIC_IRQ_CHIP
149 select IRQ_DOMAIN
150 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
153 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
156 select GENERIC_IRQ_CHIP
157 select IRQ_DOMAIN
158 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
161 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
164 select GENERIC_IRQ_CHIP
165 select IRQ_DOMAIN
171 select GENERIC_IRQ_CHIP
172 select IRQ_DOMAIN
176 select GENERIC_IRQ_CHIP
177 select IRQ_DOMAIN
181 select GENERIC_IRQ_CHIP
182 select IRQ_DOMAIN_HIERARCHY
186 select GENERIC_IRQ_CHIP
187 select IRQ_DOMAIN
191 select IRQ_DOMAIN
192 select SPARSE_IRQ
196 select ARM_GIC_V3
197 select ARM_GIC_V3_ITS
201 select GENERIC_IRQ_CHIP
202 select IRQ_DOMAIN
206 select IRQ_DOMAIN
207 select SPARSE_IRQ
212 select GENERIC_IRQ_CHIP
213 select IRQ_DOMAIN
220 will be called irq-lan966x-oic.
227 select GENERIC_IRQ_CHIP
228 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
229 select IRQ_DOMAIN
230 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
235 select IRQ_DOMAIN
236 select SPARSE_IRQ
244 select IRQ_DOMAIN
248 select GENERIC_IRQ_CHIP
249 select IRQ_DOMAIN
253 select IRQ_DOMAIN
257 select GENERIC_IRQ_CHIP
258 select IRQ_DOMAIN
261 bool "J-Core integrated AIC" if COMPILE_TEST
263 select IRQ_DOMAIN
265 Support for the J-Core integrated AIC.
269 select IRQ_DOMAIN
273 select IRQ_DOMAIN
276 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
279 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
280 select GENERIC_IRQ_CHIP
281 select IRQ_DOMAIN
284 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
288 select IRQ_DOMAIN_HIERARCHY
291 to 8 external interrupts with configurable sense select.
295 select GENERIC_IRQ_CHIP
296 select IRQ_DOMAIN_HIERARCHY
303 select GENERIC_IRQ_CHIP
304 select IRQ_DOMAIN_HIERARCHY
311 select REGMAP_IRQ
318 select REGMAP
319 select MFD_SYSCON
328 select IRQ_DOMAIN_HIERARCHY
329 select IRQ_FASTEOI_HIERARCHY_HANDLERS
333 select GENERIC_IRQ_CHIP
337 select IRQ_DOMAIN
338 select GENERIC_IRQ_CHIP
341 tristate "TS-4800 IRQ controller"
342 select IRQ_DOMAIN
346 Support for the TS-4800 FPGA IRQ controller
350 select IRQ_DOMAIN
359 select IRQ_DOMAIN
360 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
365 select IRQ_DOMAIN
388 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
389 select GENERIC_IRQ_IPI if SMP
390 select IRQ_DOMAIN_HIERARCHY
391 select MIPS_CM
402 select MFD_SYSCON
403 select GENERIC_IRQ_CHIP
412 select IRQ_DOMAIN
418 select IRQ_DOMAIN
419 select STMP_DEVICE
423 select IRQ_DOMAIN
424 select GENERIC_IRQ_CHIP
427 select IRQ_MSI_LIB
435 select IRQ_MSI_LIB
436 select GENERIC_MSI_IRQ
446 select MFD_SYSCON
450 select IRQ_MSI_IOMMU
452 select IRQ_MSI_LIB
461 select IRQ_DOMAIN_HIERARCHY
462 select GENERIC_IRQ_CHIP
468 select IRQ_DOMAIN
469 select GENERIC_IRQ_CHIP
474 select IRQ_DOMAIN_HIERARCHY
483 select IRQ_DOMAIN_HIERARCHY
491 select IRQ_DOMAIN_HIERARCHY
498 select GENERIC_IRQ_CHIP
499 select IRQ_DOMAIN
507 select IRQ_DOMAIN_HIERARCHY
516 select IRQ_DOMAIN_HIERARCHY
525 Say yes here to enable C-SKY SMP interrupt controller driver used
526 for C-SKY SMP system.
531 bool "C-SKY APB Interrupt Controller"
534 Say yes here to enable C-SKY APB interrupt controller driver used
535 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
542 select IRQ_DOMAIN
549 select IRQ_DOMAIN
558 select IRQ_DOMAIN
559 select IRQ_DOMAIN_HIERARCHY
560 select GENERIC_MSI_IRQ
561 select IRQ_MSI_LIB
564 CPU-to-CPU MSI controller. This requires a specially crafted DT
570 bool "Loongson-1 Interrupt Controller"
573 select IRQ_DOMAIN
574 select GENERIC_IRQ_CHIP
576 Support for the Loongson-1 platform Interrupt Controller.
582 select IRQ_DOMAIN_HIERARCHY
593 select IRQ_DOMAIN_HIERARCHY
594 select TI_SCI_INTA_MSI_DOMAIN
605 select IRQ_DOMAIN
607 This enables support for the PRU-ICSS Local Interrupt Controller
608 present within a PRU-ICSS subsystem present on various TI SoCs.
615 select IRQ_DOMAIN_HIERARCHY
620 select IRQ_DOMAIN_HIERARCHY
625 select GENERIC_MSI_IRQ
631 select IRQ_DOMAIN_HIERARCHY
632 select GENERIC_IRQ_MATRIX_ALLOCATOR
633 select GENERIC_MSI_IRQ
634 select IRQ_MSI_LIB
639 select IRQ_DOMAIN_HIERARCHY
640 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
646 select IRQ_DOMAIN_HIERARCHY
648 This enables support for the INTC chip found in StarFive JH8100
654 bool "RISC-V ACLINT S-mode IPI Interrupt Controller"
657 select IRQ_DOMAIN_HIERARCHY
658 select GENERIC_IRQ_IPI_MUX
660 This enables support for variants of the RISC-V ACLINT-SSWI device.
662 - T-HEAD, with compatible "thead,c900-aclint-sswi"
663 - MIPS P8700, with compatible "mips,p8700-aclint-sswi"
670 select ACLINT_SSWI
681 select GENERIC_IRQ_CHIP
682 select IRQ_DOMAIN
683 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
684 select LOONGSON_HTVEC
685 select LOONGSON_LIOINTC
686 select LOONGSON_EIOINTC
687 select LOONGSON_PCH_PIC
688 select LOONGSON_PCH_MSI
689 select LOONGSON_PCH_LPC
692 irq chip hierarchy on LoongArch platforms please read the document
693 Documentation/arch/loongarch/irq-chip-model.rst.
699 select IRQ_DOMAIN
700 select GENERIC_IRQ_CHIP
709 select IRQ_DOMAIN_HIERARCHY
710 select GENERIC_IRQ_CHIP
718 select IRQ_DOMAIN
719 select GENERIC_IRQ_CHIP
721 Support for the Loongson-3 HyperTransport PIC Controller.
727 select IRQ_DOMAIN_HIERARCHY
735 select IRQ_DOMAIN_HIERARCHY
736 select IRQ_FASTEOI_HIERARCHY_HANDLERS
745 select IRQ_DOMAIN_HIERARCHY
746 select IRQ_MSI_LIB
747 select PCI_MSI
756 select IRQ_DOMAIN_HIERARCHY
764 select IRQ_DOMAIN
765 select IRQ_DOMAIN_HIERARCHY
777 select GENERIC_IRQ_CHIP
778 select IRQ_DOMAIN
784 select GENERIC_IRQ_IPI_MUX
792 select IRQ_DOMAIN
793 select IRQ_DOMAIN_HIERARCHY
801 select IRQ_DOMAIN_HIERARCHY
802 select IRQ_MSI_LIB
803 select PCI_MSI
806 This on-chip interrupt controller enables MSI sources to be
814 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
815 chained controller, routing all interrupt source in P-Chip to
816 the primary controller on C-Chip.