Lines Matching full:iommu
17 #include "iommu.h"
116 struct intel_iommu *iommu; in iommu_regset_show() local
122 for_each_active_iommu(iommu, drhd) { in iommu_regset_show()
124 seq_puts(m, "IOMMU: Invalid base address\n"); in iommu_regset_show()
129 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in iommu_regset_show()
130 iommu->name, drhd->reg_base_addr); in iommu_regset_show()
136 raw_spin_lock_irqsave(&iommu->register_lock, flag); in iommu_regset_show()
138 value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); in iommu_regset_show()
144 value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); in iommu_regset_show()
149 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in iommu_regset_show()
217 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus) in ctx_tbl_walk() argument
239 context = iommu_context_addr(iommu, bus, devfn, 0); in ctx_tbl_walk()
248 tbl_wlk.rt_entry = &iommu->root_entry[bus]; in ctx_tbl_walk()
252 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { in ctx_tbl_walk()
263 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu) in root_tbl_walk() argument
267 spin_lock(&iommu->lock); in root_tbl_walk()
268 seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name, in root_tbl_walk()
269 (u64)virt_to_phys(iommu->root_entry)); in root_tbl_walk()
278 ctx_tbl_walk(m, iommu, bus); in root_tbl_walk()
279 spin_unlock(&iommu->lock); in root_tbl_walk()
285 struct intel_iommu *iommu; in dmar_translation_struct_show() local
289 for_each_active_iommu(iommu, drhd) { in dmar_translation_struct_show()
290 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); in dmar_translation_struct_show()
293 iommu->name); in dmar_translation_struct_show()
296 root_tbl_walk(m, iommu); in dmar_translation_struct_show()
353 struct intel_iommu *iommu; in domain_translation_struct_show() local
361 for_each_active_iommu(iommu, drhd) { in domain_translation_struct_show()
366 if (seg != iommu->segment) in domain_translation_struct_show()
369 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); in domain_translation_struct_show()
372 iommu->name); in domain_translation_struct_show()
375 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) in domain_translation_struct_show()
381 * The iommu->lock is held across the callback, which will in domain_translation_struct_show()
389 spin_lock(&iommu->lock); in domain_translation_struct_show()
391 context = iommu_context_addr(iommu, bus, devfn, 0); in domain_translation_struct_show()
443 iommu->segment, bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); in domain_translation_struct_show()
456 spin_unlock(&iommu->lock); in domain_translation_struct_show()
483 struct intel_iommu *iommu) in invalidation_queue_entry_show() argument
485 int index, shift = qi_shift(iommu); in invalidation_queue_entry_show()
489 if (ecap_smts(iommu->ecap)) in invalidation_queue_entry_show()
496 desc = iommu->qi->desc + offset; in invalidation_queue_entry_show()
497 if (ecap_smts(iommu->ecap)) in invalidation_queue_entry_show()
501 iommu->qi->desc_status[index]); in invalidation_queue_entry_show()
505 iommu->qi->desc_status[index]); in invalidation_queue_entry_show()
512 struct intel_iommu *iommu; in invalidation_queue_show() local
518 for_each_active_iommu(iommu, drhd) { in invalidation_queue_show()
519 qi = iommu->qi; in invalidation_queue_show()
520 shift = qi_shift(iommu); in invalidation_queue_show()
522 if (!qi || !ecap_qis(iommu->ecap)) in invalidation_queue_show()
525 seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name); in invalidation_queue_show()
530 dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift, in invalidation_queue_show()
531 dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift); in invalidation_queue_show()
532 invalidation_queue_entry_show(m, iommu); in invalidation_queue_show()
544 struct intel_iommu *iommu) in ir_tbl_remap_entry_show() argument
554 ri_entry = &iommu->ir_table->base[idx]; in ir_tbl_remap_entry_show()
568 struct intel_iommu *iommu) in ir_tbl_posted_entry_show() argument
578 pi_entry = &iommu->ir_table->base[idx]; in ir_tbl_posted_entry_show()
600 struct intel_iommu *iommu; in ir_translation_struct_show() local
605 for_each_active_iommu(iommu, drhd) { in ir_translation_struct_show()
606 if (!ecap_ir_support(iommu->ecap)) in ir_translation_struct_show()
609 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n", in ir_translation_struct_show()
610 iommu->name); in ir_translation_struct_show()
612 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); in ir_translation_struct_show()
613 if (iommu->ir_table && (sts & DMA_GSTS_IRES)) { in ir_translation_struct_show()
614 irta = virt_to_phys(iommu->ir_table->base); in ir_translation_struct_show()
616 ir_tbl_remap_entry_show(m, iommu); in ir_translation_struct_show()
625 for_each_active_iommu(iommu, drhd) { in ir_translation_struct_show()
626 if (!cap_pi_support(iommu->cap)) in ir_translation_struct_show()
629 seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n", in ir_translation_struct_show()
630 iommu->name); in ir_translation_struct_show()
632 if (iommu->ir_table) { in ir_translation_struct_show()
633 irta = virt_to_phys(iommu->ir_table->base); in ir_translation_struct_show()
635 ir_tbl_posted_entry_show(m, iommu); in ir_translation_struct_show()
648 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu, in latency_show_one() argument
653 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", in latency_show_one()
654 iommu->name, drhd->reg_base_addr); in latency_show_one()
656 ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE); in latency_show_one()
667 struct intel_iommu *iommu; in latency_show() local
670 for_each_active_iommu(iommu, drhd) in latency_show()
671 latency_show_one(m, iommu, drhd); in latency_show()
687 struct intel_iommu *iommu; in dmar_perf_latency_write() local
705 for_each_active_iommu(iommu, drhd) { in dmar_perf_latency_write()
706 dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB); in dmar_perf_latency_write()
707 dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB); in dmar_perf_latency_write()
708 dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC); in dmar_perf_latency_write()
714 for_each_active_iommu(iommu, drhd) in dmar_perf_latency_write()
715 dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB); in dmar_perf_latency_write()
720 for_each_active_iommu(iommu, drhd) in dmar_perf_latency_write()
721 dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB); in dmar_perf_latency_write()
726 for_each_active_iommu(iommu, drhd) in dmar_perf_latency_write()
727 dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC); in dmar_perf_latency_write()
768 * /sys/kernel/debug/iommu/intel/0000:00:01.0/domain_translation_struct
788 * /sys/kernel/debug/iommu/intel/0000:00:01.0/1/domain_translation_struct