1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
28 #include <soc/qcom/qcom-spmi-pmic.h>
30 #define DRIVER_NAME "qcom-spmi-rradc"
32 #define RR_ADC_EN_CTL 0x46
33 #define RR_ADC_SKIN_TEMP_LSB 0x50
34 #define RR_ADC_SKIN_TEMP_MSB 0x51
35 #define RR_ADC_CTL 0x52
37 #define RR_ADC_LOG 0x53
38 #define RR_ADC_LOG_CLR_CTRL BIT(0)
40 #define RR_ADC_FAKE_BATT_LOW_LSB 0x58
41 #define RR_ADC_FAKE_BATT_LOW_MSB 0x59
42 #define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A
43 #define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B
45 #define RR_ADC_BATT_ID_CTRL 0x60
46 #define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0)
47 #define RR_ADC_BATT_ID_TRIGGER 0x61
48 #define RR_ADC_BATT_ID_STS 0x62
49 #define RR_ADC_BATT_ID_CFG 0x63
51 #define RR_ADC_BATT_ID_5_LSB 0x66
52 #define RR_ADC_BATT_ID_5_MSB 0x67
53 #define RR_ADC_BATT_ID_15_LSB 0x68
54 #define RR_ADC_BATT_ID_15_MSB 0x69
55 #define RR_ADC_BATT_ID_150_LSB 0x6A
56 #define RR_ADC_BATT_ID_150_MSB 0x6B
58 #define RR_ADC_BATT_THERM_CTRL 0x70
59 #define RR_ADC_BATT_THERM_TRIGGER 0x71
60 #define RR_ADC_BATT_THERM_STS 0x72
61 #define RR_ADC_BATT_THERM_CFG 0x73
62 #define RR_ADC_BATT_THERM_LSB 0x74
63 #define RR_ADC_BATT_THERM_MSB 0x75
64 #define RR_ADC_BATT_THERM_FREQ 0x76
66 #define RR_ADC_AUX_THERM_CTRL 0x80
67 #define RR_ADC_AUX_THERM_TRIGGER 0x81
68 #define RR_ADC_AUX_THERM_STS 0x82
69 #define RR_ADC_AUX_THERM_CFG 0x83
70 #define RR_ADC_AUX_THERM_LSB 0x84
71 #define RR_ADC_AUX_THERM_MSB 0x85
73 #define RR_ADC_SKIN_HOT 0x86
74 #define RR_ADC_SKIN_TOO_HOT 0x87
76 #define RR_ADC_AUX_THERM_C1 0x88
77 #define RR_ADC_AUX_THERM_C2 0x89
78 #define RR_ADC_AUX_THERM_C3 0x8A
79 #define RR_ADC_AUX_THERM_HALF_RANGE 0x8B
81 #define RR_ADC_USB_IN_V_CTRL 0x90
82 #define RR_ADC_USB_IN_V_TRIGGER 0x91
83 #define RR_ADC_USB_IN_V_STS 0x92
84 #define RR_ADC_USB_IN_V_LSB 0x94
85 #define RR_ADC_USB_IN_V_MSB 0x95
86 #define RR_ADC_USB_IN_I_CTRL 0x98
87 #define RR_ADC_USB_IN_I_TRIGGER 0x99
88 #define RR_ADC_USB_IN_I_STS 0x9A
89 #define RR_ADC_USB_IN_I_LSB 0x9C
90 #define RR_ADC_USB_IN_I_MSB 0x9D
92 #define RR_ADC_DC_IN_V_CTRL 0xA0
93 #define RR_ADC_DC_IN_V_TRIGGER 0xA1
94 #define RR_ADC_DC_IN_V_STS 0xA2
95 #define RR_ADC_DC_IN_V_LSB 0xA4
96 #define RR_ADC_DC_IN_V_MSB 0xA5
97 #define RR_ADC_DC_IN_I_CTRL 0xA8
98 #define RR_ADC_DC_IN_I_TRIGGER 0xA9
99 #define RR_ADC_DC_IN_I_STS 0xAA
100 #define RR_ADC_DC_IN_I_LSB 0xAC
101 #define RR_ADC_DC_IN_I_MSB 0xAD
103 #define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0
104 #define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1
105 #define RR_ADC_PMI_DIE_TEMP_STS 0xB2
106 #define RR_ADC_PMI_DIE_TEMP_CFG 0xB3
107 #define RR_ADC_PMI_DIE_TEMP_LSB 0xB4
108 #define RR_ADC_PMI_DIE_TEMP_MSB 0xB5
110 #define RR_ADC_CHARGER_TEMP_CTRL 0xB8
111 #define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9
112 #define RR_ADC_CHARGER_TEMP_STS 0xBA
113 #define RR_ADC_CHARGER_TEMP_CFG 0xBB
114 #define RR_ADC_CHARGER_TEMP_LSB 0xBC
115 #define RR_ADC_CHARGER_TEMP_MSB 0xBD
116 #define RR_ADC_CHARGER_HOT 0xBE
117 #define RR_ADC_CHARGER_TOO_HOT 0xBF
119 #define RR_ADC_GPIO_CTRL 0xC0
120 #define RR_ADC_GPIO_TRIGGER 0xC1
121 #define RR_ADC_GPIO_STS 0xC2
122 #define RR_ADC_GPIO_LSB 0xC4
123 #define RR_ADC_GPIO_MSB 0xC5
125 #define RR_ADC_ATEST_CTRL 0xC8
126 #define RR_ADC_ATEST_TRIGGER 0xC9
127 #define RR_ADC_ATEST_STS 0xCA
128 #define RR_ADC_ATEST_LSB 0xCC
129 #define RR_ADC_ATEST_MSB 0xCD
130 #define RR_ADC_SEC_ACCESS 0xD0
132 #define RR_ADC_PERPH_RESET_CTL2 0xD9
133 #define RR_ADC_PERPH_RESET_CTL3 0xDA
134 #define RR_ADC_PERPH_RESET_CTL4 0xDB
135 #define RR_ADC_INT_TEST1 0xE0
136 #define RR_ADC_INT_TEST_VAL 0xE1
138 #define RR_ADC_TM_TRIGGER_CTRLS 0xE2
139 #define RR_ADC_TM_ADC_CTRLS 0xE3
140 #define RR_ADC_TM_CNL_CTRL 0xE4
141 #define RR_ADC_TM_BATT_ID_CTRL 0xE5
142 #define RR_ADC_TM_THERM_CTRL 0xE6
143 #define RR_ADC_TM_CONV_STS 0xE7
144 #define RR_ADC_TM_ADC_READ_LSB 0xE8
145 #define RR_ADC_TM_ADC_READ_MSB 0xE9
146 #define RR_ADC_TM_ATEST_MUX_1 0xEA
147 #define RR_ADC_TM_ATEST_MUX_2 0xEB
148 #define RR_ADC_TM_REFERENCES 0xED
149 #define RR_ADC_TM_MISC_CTL 0xEE
150 #define RR_ADC_TM_RR_CTRL 0xEF
153 #define RR_ADC_TRIGGER_CTL BIT(0)
193 #define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0)
203 	RR_ADC_BATT_ID = 0,
219  * struct rradc_channel - rradc channel data
253 static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 };
259 	int ret, retry_cnt = 0;  in rradc_read()
263 		dev_err(chip->dev,  in rradc_read()
266 		return -EINVAL;  in rradc_read()
270 		ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf,  in rradc_read()
272 		if (ret < 0) {  in rradc_read()
273 			dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,  in rradc_read()
278 		ret = regmap_bulk_read(chip->regmap, chip->base + addr,  in rradc_read()
280 		if (ret < 0) {  in rradc_read()
281 			dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,  in rradc_read()
286 		if (memcmp(buf, data_check, len) != 0) {  in rradc_read()
288 			dev_dbg(chip->dev,  in rradc_read()
298 		dev_err(chip->dev, "Retry exceeded for coherency check\n");  in rradc_read()
306 	if (chip->pmic->subtype == PM660_SUBTYPE) {  in rradc_get_fab_coeff()
307 		switch (chip->pmic->fab_id) {  in rradc_get_fab_coeff()
311 			return 0;  in rradc_get_fab_coeff()
315 			return 0;  in rradc_get_fab_coeff()
320 	} else if (chip->pmic->subtype == PMI8998_SUBTYPE) {  in rradc_get_fab_coeff()
321 		switch (chip->pmic->fab_id) {  in rradc_get_fab_coeff()
325 			return 0;  in rradc_get_fab_coeff()
329 			return 0;  in rradc_get_fab_coeff()
331 			return -EINVAL;  in rradc_get_fab_coeff()
335 	return -EINVAL;  in rradc_get_fab_coeff()
348 	current_value = chip->batt_id_data;  in rradc_post_process_batt_id()
353 	return 0;  in rradc_post_process_batt_id()
361 	ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_LOG,  in rradc_enable_continuous_mode()
363 	if (ret < 0) {  in rradc_enable_continuous_mode()
364 		dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret);  in rradc_enable_continuous_mode()
368 	ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_LOG,  in rradc_enable_continuous_mode()
370 	if (ret < 0) {  in rradc_enable_continuous_mode()
371 		dev_err(chip->dev, "log ctrl update to not clear failed:%d\n",  in rradc_enable_continuous_mode()
377 	ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_CTL,  in rradc_enable_continuous_mode()
379 	if (ret < 0)  in rradc_enable_continuous_mode()
380 		dev_err(chip->dev, "Update to continuous mode failed:%d\n",  in rradc_enable_continuous_mode()
391 	ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_CTL,  in rradc_disable_continuous_mode()
393 	if (ret < 0)  in rradc_disable_continuous_mode()
394 		dev_err(chip->dev, "Update to non-continuous mode failed:%d\n",  in rradc_disable_continuous_mode()
417 	ret = regmap_read(chip->regmap, chip->base + chan->status, &status);  in rradc_is_ready()
418 	if (ret < 0 || !(status & mask))  in rradc_is_ready()
431 	if (chan->trigger_mask == 0) {  in rradc_read_status_in_cont_mode()
432 		dev_err(chip->dev, "Channel doesn't have a trigger mask\n");  in rradc_read_status_in_cont_mode()
433 		return -EINVAL;  in rradc_read_status_in_cont_mode()
436 	ret = regmap_set_bits(chip->regmap, chip->base + chan->trigger_addr,  in rradc_read_status_in_cont_mode()
437 			      chan->trigger_mask);  in rradc_read_status_in_cont_mode()
438 	if (ret < 0) {  in rradc_read_status_in_cont_mode()
439 		dev_err(chip->dev,  in rradc_read_status_in_cont_mode()
441 			iio_chan->extend_name, ret);  in rradc_read_status_in_cont_mode()
446 	if (ret < 0) {  in rradc_read_status_in_cont_mode()
447 		dev_err(chip->dev, "Failed to switch to continuous mode\n");  in rradc_read_status_in_cont_mode()
456 	for (i = 0; i < 5; i++) {  in rradc_read_status_in_cont_mode()
463 		dev_err(chip->dev, "Channel '%s' is not ready\n",  in rradc_read_status_in_cont_mode()
464 			iio_chan->extend_name);  in rradc_read_status_in_cont_mode()
465 		ret = -ETIMEDOUT;  in rradc_read_status_in_cont_mode()
471 	regmap_clear_bits(chip->regmap, chip->base + chan->trigger_addr,  in rradc_read_status_in_cont_mode()
472 			  chan->trigger_mask);  in rradc_read_status_in_cont_mode()
483 	ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,  in rradc_prepare_batt_id_conversion()
485 	if (ret < 0) {  in rradc_prepare_batt_id_conversion()
486 		dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret);  in rradc_prepare_batt_id_conversion()
490 	ret = regmap_set_bits(chip->regmap,  in rradc_prepare_batt_id_conversion()
491 			      chip->base + RR_ADC_BATT_ID_TRIGGER,  in rradc_prepare_batt_id_conversion()
493 	if (ret < 0) {  in rradc_prepare_batt_id_conversion()
494 		dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret);  in rradc_prepare_batt_id_conversion()
501 	regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER,  in rradc_prepare_batt_id_conversion()
505 	regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,  in rradc_prepare_batt_id_conversion()
519 	mutex_lock(&chip->conversion_lock);  in rradc_do_conversion()
524 		if (ret < 0) {  in rradc_do_conversion()
525 			dev_err(chip->dev, "Battery ID conversion failed:%d\n",  in rradc_do_conversion()
534 		if (ret < 0) {  in rradc_do_conversion()
535 			dev_err(chip->dev,  in rradc_do_conversion()
547 			dev_dbg(chip->dev, "channel '%s' is not ready\n",  in rradc_do_conversion()
548 				iio_chan->extend_name);  in rradc_do_conversion()
549 			ret = -ENODATA;  in rradc_do_conversion()
555 	ret = rradc_read(chip, chan->lsb, buf, chan->size);  in rradc_do_conversion()
557 		dev_err(chip->dev, "read data failed\n");  in rradc_do_conversion()
568 		u16 batt_id_5 = le16_to_cpu(buf[0]);  in rradc_do_conversion()
571 			dev_err(chip->dev,  in rradc_do_conversion()
573 			ret = -EINVAL;  in rradc_do_conversion()
579 			chip->batt_id_data = 150;  in rradc_do_conversion()
582 			chip->batt_id_data = 15;  in rradc_do_conversion()
585 			chip->batt_id_data = 5;  in rradc_do_conversion()
590 		 * We can rely on the second byte being 0 for 1-byte channels.  in rradc_do_conversion()
592 		*data = le16_to_cpu(buf[0]);  in rradc_do_conversion()
596 	mutex_unlock(&chip->conversion_lock);  in rradc_do_conversion()
608 	if (ret < 0) {  in rradc_read_scale()
609 		dev_err(chip->dev, "Unable to get fab id coefficients\n");  in rradc_read_scale()
610 		return -EINVAL;  in rradc_read_scale()
641 		*val = -RR_ADC_TEMP_FS_VOLTAGE_NUM;  in rradc_read_scale()
654 		return -EINVAL;  in rradc_read_scale()
676 		if (ret < 0) {  in rradc_read_offset()
677 			dev_err(chip->dev,  in rradc_read_offset()
679 			return -EINVAL;  in rradc_read_offset()
681 		offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN *  in rradc_read_offset()
695 		 * The -1 is to compensate for lost precision.  in rradc_read_offset()
696 		 * It should actually be -0.7906976744186046.  in rradc_read_offset()
700 		*val = (int)(offset1 - offset2 - 1);  in rradc_read_offset()
703 		offset1 = -RR_ADC_DIE_TEMP_OFFSET *  in rradc_read_offset()
708 		offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *  in rradc_read_offset()
715 		 * The result is -339, it should be -338.69789, this results  in rradc_read_offset()
717 		 * -0.004 - -0.0175 degrees C  in rradc_read_offset()
719 		*val = (int)(offset1 - offset2);  in rradc_read_offset()
724 	return -EINVAL;  in rradc_read_offset()
736 	if (chan_spec->address >= RR_ADC_CHAN_MAX) {  in rradc_read_raw()
737 		dev_err(chip->dev, "Invalid channel index:%lu\n",  in rradc_read_raw()
738 			chan_spec->address);  in rradc_read_raw()
739 		return -EINVAL;  in rradc_read_raw()
744 		return rradc_read_scale(chip, chan_spec->address, val, val2);  in rradc_read_raw()
746 		return rradc_read_offset(chip, chan_spec->address, val);  in rradc_read_raw()
748 		ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);  in rradc_read_raw()
749 		if (ret < 0)  in rradc_read_raw()
755 		chan = &rradc_chans[chan_spec->address];  in rradc_read_raw()
756 		if (!chan->scale_fn)  in rradc_read_raw()
757 			return -EINVAL;  in rradc_read_raw()
758 		ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);  in rradc_read_raw()
759 		if (ret < 0)  in rradc_read_raw()
762 		*val = chan->scale_fn(chip, adc_code, val);  in rradc_read_raw()
765 		return -EINVAL;  in rradc_read_raw()
773 			rradc_chans[chan->address].label);  in rradc_read_label()
789 		.trigger_mask = BIT(0),
854 		.channel = 0,
855 		.indexed = 1,
860 		.channel = 0,
861 		.indexed = 1,
869 		.indexed = 1,
875 		.channel = 0,
876 		.indexed = 1,
882 		.channel = 0,
883 		.indexed = 1,
890 		.indexed = 1,
897 		.indexed = 1,
905 		.indexed = 1,
913 		.indexed = 1,
920 		.indexed = 1,
926 	struct device *dev = &pdev->dev;  in rradc_probe()
933 		return -ENOMEM;  in rradc_probe()
936 	chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);  in rradc_probe()
937 	if (!chip->regmap) {  in rradc_probe()
939 		return -EINVAL;  in rradc_probe()
942 	chip->dev = dev;  in rradc_probe()
943 	mutex_init(&chip->conversion_lock);  in rradc_probe()
945 	ret = device_property_read_u32(dev, "reg", &chip->base);  in rradc_probe()
946 	if (ret < 0) {  in rradc_probe()
947 		dev_err(chip->dev, "Couldn't find reg address, ret = %d\n",  in rradc_probe()
952 	batt_id_delay = -1;  in rradc_probe()
953 	ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms",  in rradc_probe()
956 		for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) {  in rradc_probe()
961 			batt_id_delay = -1;  in rradc_probe()
964 	if (batt_id_delay >= 0) {  in rradc_probe()
966 		ret = regmap_set_bits(chip->regmap,  in rradc_probe()
967 				      chip->base + RR_ADC_BATT_ID_CFG,  in rradc_probe()
969 		if (ret < 0) {  in rradc_probe()
970 			dev_err(chip->dev,  in rradc_probe()
977 	chip->pmic = qcom_pmic_get(chip->dev);  in rradc_probe()
978 	if (IS_ERR(chip->pmic)) {  in rradc_probe()
979 		dev_err(chip->dev, "Unable to get reference to PMIC device\n");  in rradc_probe()
980 		return PTR_ERR(chip->pmic);  in rradc_probe()
983 	switch (chip->pmic->subtype) {  in rradc_probe()
985 		indio_dev->name = "pmi8998-rradc";  in rradc_probe()
988 		indio_dev->name = "pm660-rradc";  in rradc_probe()
991 		indio_dev->name = DRIVER_NAME;  in rradc_probe()
994 	indio_dev->modes = INDIO_DIRECT_MODE;  in rradc_probe()
995 	indio_dev->info = &rradc_info;  in rradc_probe()
996 	indio_dev->channels = rradc_iio_chans;  in rradc_probe()
997 	indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans);  in rradc_probe()
1003 	{ .compatible = "qcom,pm660-rradc" },
1004 	{ .compatible = "qcom,pmi8998-rradc" },