1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022 Linaro Limited. 5 * Author: Caleb Connolly <caleb.connolly@linaro.org> 6 * 7 * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/delay.h> 12 #include <linux/kernel.h> 13 #include <linux/math64.h> 14 #include <linux/module.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/platform_device.h> 17 #include <linux/property.h> 18 #include <linux/regmap.h> 19 #include <linux/spmi.h> 20 #include <linux/types.h> 21 #include <linux/units.h> 22 23 #include <asm/unaligned.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/types.h> 27 28 #include <soc/qcom/qcom-spmi-pmic.h> 29 30 #define DRIVER_NAME "qcom-spmi-rradc" 31 32 #define RR_ADC_EN_CTL 0x46 33 #define RR_ADC_SKIN_TEMP_LSB 0x50 34 #define RR_ADC_SKIN_TEMP_MSB 0x51 35 #define RR_ADC_CTL 0x52 36 #define RR_ADC_CTL_CONTINUOUS_SEL BIT(3) 37 #define RR_ADC_LOG 0x53 38 #define RR_ADC_LOG_CLR_CTRL BIT(0) 39 40 #define RR_ADC_FAKE_BATT_LOW_LSB 0x58 41 #define RR_ADC_FAKE_BATT_LOW_MSB 0x59 42 #define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A 43 #define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B 44 45 #define RR_ADC_BATT_ID_CTRL 0x60 46 #define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0) 47 #define RR_ADC_BATT_ID_TRIGGER 0x61 48 #define RR_ADC_BATT_ID_STS 0x62 49 #define RR_ADC_BATT_ID_CFG 0x63 50 #define BATT_ID_SETTLE_MASK GENMASK(7, 5) 51 #define RR_ADC_BATT_ID_5_LSB 0x66 52 #define RR_ADC_BATT_ID_5_MSB 0x67 53 #define RR_ADC_BATT_ID_15_LSB 0x68 54 #define RR_ADC_BATT_ID_15_MSB 0x69 55 #define RR_ADC_BATT_ID_150_LSB 0x6A 56 #define RR_ADC_BATT_ID_150_MSB 0x6B 57 58 #define RR_ADC_BATT_THERM_CTRL 0x70 59 #define RR_ADC_BATT_THERM_TRIGGER 0x71 60 #define RR_ADC_BATT_THERM_STS 0x72 61 #define RR_ADC_BATT_THERM_CFG 0x73 62 #define RR_ADC_BATT_THERM_LSB 0x74 63 #define RR_ADC_BATT_THERM_MSB 0x75 64 #define RR_ADC_BATT_THERM_FREQ 0x76 65 66 #define RR_ADC_AUX_THERM_CTRL 0x80 67 #define RR_ADC_AUX_THERM_TRIGGER 0x81 68 #define RR_ADC_AUX_THERM_STS 0x82 69 #define RR_ADC_AUX_THERM_CFG 0x83 70 #define RR_ADC_AUX_THERM_LSB 0x84 71 #define RR_ADC_AUX_THERM_MSB 0x85 72 73 #define RR_ADC_SKIN_HOT 0x86 74 #define RR_ADC_SKIN_TOO_HOT 0x87 75 76 #define RR_ADC_AUX_THERM_C1 0x88 77 #define RR_ADC_AUX_THERM_C2 0x89 78 #define RR_ADC_AUX_THERM_C3 0x8A 79 #define RR_ADC_AUX_THERM_HALF_RANGE 0x8B 80 81 #define RR_ADC_USB_IN_V_CTRL 0x90 82 #define RR_ADC_USB_IN_V_TRIGGER 0x91 83 #define RR_ADC_USB_IN_V_STS 0x92 84 #define RR_ADC_USB_IN_V_LSB 0x94 85 #define RR_ADC_USB_IN_V_MSB 0x95 86 #define RR_ADC_USB_IN_I_CTRL 0x98 87 #define RR_ADC_USB_IN_I_TRIGGER 0x99 88 #define RR_ADC_USB_IN_I_STS 0x9A 89 #define RR_ADC_USB_IN_I_LSB 0x9C 90 #define RR_ADC_USB_IN_I_MSB 0x9D 91 92 #define RR_ADC_DC_IN_V_CTRL 0xA0 93 #define RR_ADC_DC_IN_V_TRIGGER 0xA1 94 #define RR_ADC_DC_IN_V_STS 0xA2 95 #define RR_ADC_DC_IN_V_LSB 0xA4 96 #define RR_ADC_DC_IN_V_MSB 0xA5 97 #define RR_ADC_DC_IN_I_CTRL 0xA8 98 #define RR_ADC_DC_IN_I_TRIGGER 0xA9 99 #define RR_ADC_DC_IN_I_STS 0xAA 100 #define RR_ADC_DC_IN_I_LSB 0xAC 101 #define RR_ADC_DC_IN_I_MSB 0xAD 102 103 #define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0 104 #define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1 105 #define RR_ADC_PMI_DIE_TEMP_STS 0xB2 106 #define RR_ADC_PMI_DIE_TEMP_CFG 0xB3 107 #define RR_ADC_PMI_DIE_TEMP_LSB 0xB4 108 #define RR_ADC_PMI_DIE_TEMP_MSB 0xB5 109 110 #define RR_ADC_CHARGER_TEMP_CTRL 0xB8 111 #define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9 112 #define RR_ADC_CHARGER_TEMP_STS 0xBA 113 #define RR_ADC_CHARGER_TEMP_CFG 0xBB 114 #define RR_ADC_CHARGER_TEMP_LSB 0xBC 115 #define RR_ADC_CHARGER_TEMP_MSB 0xBD 116 #define RR_ADC_CHARGER_HOT 0xBE 117 #define RR_ADC_CHARGER_TOO_HOT 0xBF 118 119 #define RR_ADC_GPIO_CTRL 0xC0 120 #define RR_ADC_GPIO_TRIGGER 0xC1 121 #define RR_ADC_GPIO_STS 0xC2 122 #define RR_ADC_GPIO_LSB 0xC4 123 #define RR_ADC_GPIO_MSB 0xC5 124 125 #define RR_ADC_ATEST_CTRL 0xC8 126 #define RR_ADC_ATEST_TRIGGER 0xC9 127 #define RR_ADC_ATEST_STS 0xCA 128 #define RR_ADC_ATEST_LSB 0xCC 129 #define RR_ADC_ATEST_MSB 0xCD 130 #define RR_ADC_SEC_ACCESS 0xD0 131 132 #define RR_ADC_PERPH_RESET_CTL2 0xD9 133 #define RR_ADC_PERPH_RESET_CTL3 0xDA 134 #define RR_ADC_PERPH_RESET_CTL4 0xDB 135 #define RR_ADC_INT_TEST1 0xE0 136 #define RR_ADC_INT_TEST_VAL 0xE1 137 138 #define RR_ADC_TM_TRIGGER_CTRLS 0xE2 139 #define RR_ADC_TM_ADC_CTRLS 0xE3 140 #define RR_ADC_TM_CNL_CTRL 0xE4 141 #define RR_ADC_TM_BATT_ID_CTRL 0xE5 142 #define RR_ADC_TM_THERM_CTRL 0xE6 143 #define RR_ADC_TM_CONV_STS 0xE7 144 #define RR_ADC_TM_ADC_READ_LSB 0xE8 145 #define RR_ADC_TM_ADC_READ_MSB 0xE9 146 #define RR_ADC_TM_ATEST_MUX_1 0xEA 147 #define RR_ADC_TM_ATEST_MUX_2 0xEB 148 #define RR_ADC_TM_REFERENCES 0xED 149 #define RR_ADC_TM_MISC_CTL 0xEE 150 #define RR_ADC_TM_RR_CTRL 0xEF 151 152 #define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7) 153 #define RR_ADC_TRIGGER_CTL BIT(0) 154 155 #define RR_ADC_BATT_ID_RANGE 820 156 157 #define RR_ADC_BITS 10 158 #define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS) 159 #define RR_ADC_FS_VOLTAGE_MV 2500 160 161 /* BATT_THERM 0.25K/LSB */ 162 #define RR_ADC_BATT_THERM_LSB_K 4 163 164 #define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000 165 #define RR_ADC_TEMP_FS_VOLTAGE_DEN 3 166 #define RR_ADC_DIE_TEMP_OFFSET 601400 167 #define RR_ADC_DIE_TEMP_SLOPE 2 168 #define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000 169 170 #define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168 171 #define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784 172 #define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433 173 #define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655 174 #define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001 175 #define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403 176 #define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898 177 #define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596 178 #define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779 179 #define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496 180 #define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000 181 #define RR_ADC_CHG_THRESHOLD_SCALE 4 182 183 #define RR_ADC_VOLT_INPUT_FACTOR 8 184 #define RR_ADC_CURR_INPUT_FACTOR 2000 185 #define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886 186 #define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9 187 #define RR_ADC_CURR_USBIN_660_UV_VAL 579500 188 189 #define RR_ADC_GPIO_FS_RANGE 5000 190 #define RR_ADC_COHERENT_CHECK_RETRY 5 191 #define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16 192 193 #define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0) 194 #define RR_ADC_STS_CHANNEL_STS BIT(1) 195 196 #define RR_ADC_TP_REV_VERSION1 21 197 #define RR_ADC_TP_REV_VERSION2 29 198 #define RR_ADC_TP_REV_VERSION3 32 199 200 #define RRADC_BATT_ID_DELAY_MAX 8 201 202 enum rradc_channel_id { 203 RR_ADC_BATT_ID = 0, 204 RR_ADC_BATT_THERM, 205 RR_ADC_SKIN_TEMP, 206 RR_ADC_USBIN_I, 207 RR_ADC_USBIN_V, 208 RR_ADC_DCIN_I, 209 RR_ADC_DCIN_V, 210 RR_ADC_DIE_TEMP, 211 RR_ADC_CHG_TEMP, 212 RR_ADC_GPIO, 213 RR_ADC_CHAN_MAX 214 }; 215 216 struct rradc_chip; 217 218 /** 219 * struct rradc_channel - rradc channel data 220 * @label: channel label 221 * @lsb: Channel least significant byte 222 * @status: Channel status address 223 * @size: number of bytes to read 224 * @trigger_addr: Trigger address, trigger is only used on some channels 225 * @trigger_mask: Trigger mask 226 * @scale_fn: Post process callback for channels which can't be exposed 227 * as offset + scale. 228 */ 229 struct rradc_channel { 230 const char *label; 231 u8 lsb; 232 u8 status; 233 int size; 234 int trigger_addr; 235 int trigger_mask; 236 int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result); 237 }; 238 239 struct rradc_chip { 240 struct device *dev; 241 const struct qcom_spmi_pmic *pmic; 242 /* 243 * Lock held while doing channel conversion 244 * involving multiple register read/writes 245 */ 246 struct mutex conversion_lock; 247 struct regmap *regmap; 248 u32 base; 249 int batt_id_delay; 250 u16 batt_id_data; 251 }; 252 253 static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 }; 254 static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX]; 255 static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX]; 256 257 static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len) 258 { 259 int ret, retry_cnt = 0; 260 __le16 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN / 2]; 261 262 if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) { 263 dev_err(chip->dev, 264 "Can't read more than %d bytes, but asked to read %d bytes.\n", 265 RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len); 266 return -EINVAL; 267 } 268 269 while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) { 270 ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf, 271 len); 272 if (ret < 0) { 273 dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, 274 ret); 275 return ret; 276 } 277 278 ret = regmap_bulk_read(chip->regmap, chip->base + addr, 279 data_check, len); 280 if (ret < 0) { 281 dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr, 282 ret); 283 return ret; 284 } 285 286 if (memcmp(buf, data_check, len) != 0) { 287 retry_cnt++; 288 dev_dbg(chip->dev, 289 "coherent read error, retry_cnt:%d\n", 290 retry_cnt); 291 continue; 292 } 293 294 break; 295 } 296 297 if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY) 298 dev_err(chip->dev, "Retry exceeded for coherency check\n"); 299 300 return ret; 301 } 302 303 static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset, 304 int64_t *slope) 305 { 306 if (chip->pmic->subtype == PM660_SUBTYPE) { 307 switch (chip->pmic->fab_id) { 308 case PM660_FAB_ID_GF: 309 *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV; 310 *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C; 311 return 0; 312 case PM660_FAB_ID_TSMC: 313 *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV; 314 *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C; 315 return 0; 316 default: 317 *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV; 318 *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C; 319 } 320 } else if (chip->pmic->subtype == PMI8998_SUBTYPE) { 321 switch (chip->pmic->fab_id) { 322 case PMI8998_FAB_ID_GF: 323 *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV; 324 *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C; 325 return 0; 326 case PMI8998_FAB_ID_SMIC: 327 *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV; 328 *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C; 329 return 0; 330 default: 331 return -EINVAL; 332 } 333 } 334 335 return -EINVAL; 336 } 337 338 /* 339 * These functions explicitly cast int64_t to int. 340 * They will never overflow, as the values are small enough. 341 */ 342 static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code, 343 int *result_ohms) 344 { 345 uint32_t current_value; 346 int64_t r_id; 347 348 current_value = chip->batt_id_data; 349 r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV); 350 r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value)); 351 *result_ohms = (int)(r_id * MILLI); 352 353 return 0; 354 } 355 356 static int rradc_enable_continuous_mode(struct rradc_chip *chip) 357 { 358 int ret; 359 360 /* Clear channel log */ 361 ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_LOG, 362 RR_ADC_LOG_CLR_CTRL); 363 if (ret < 0) { 364 dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret); 365 return ret; 366 } 367 368 ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_LOG, 369 RR_ADC_LOG_CLR_CTRL); 370 if (ret < 0) { 371 dev_err(chip->dev, "log ctrl update to not clear failed:%d\n", 372 ret); 373 return ret; 374 } 375 376 /* Switch to continuous mode */ 377 ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_CTL, 378 RR_ADC_CTL_CONTINUOUS_SEL); 379 if (ret < 0) 380 dev_err(chip->dev, "Update to continuous mode failed:%d\n", 381 ret); 382 383 return ret; 384 } 385 386 static int rradc_disable_continuous_mode(struct rradc_chip *chip) 387 { 388 int ret; 389 390 /* Switch to non continuous mode */ 391 ret = regmap_clear_bits(chip->regmap, chip->base + RR_ADC_CTL, 392 RR_ADC_CTL_CONTINUOUS_SEL); 393 if (ret < 0) 394 dev_err(chip->dev, "Update to non-continuous mode failed:%d\n", 395 ret); 396 397 return ret; 398 } 399 400 static bool rradc_is_ready(struct rradc_chip *chip, 401 enum rradc_channel_id chan_address) 402 { 403 const struct rradc_channel *chan = &rradc_chans[chan_address]; 404 int ret; 405 unsigned int status, mask; 406 407 /* BATT_ID STS bit does not get set initially */ 408 switch (chan_address) { 409 case RR_ADC_BATT_ID: 410 mask = RR_ADC_STS_CHANNEL_STS; 411 break; 412 default: 413 mask = RR_ADC_STS_CHANNEL_READING_MASK; 414 break; 415 } 416 417 ret = regmap_read(chip->regmap, chip->base + chan->status, &status); 418 if (ret < 0 || !(status & mask)) 419 return false; 420 421 return true; 422 } 423 424 static int rradc_read_status_in_cont_mode(struct rradc_chip *chip, 425 enum rradc_channel_id chan_address) 426 { 427 const struct rradc_channel *chan = &rradc_chans[chan_address]; 428 const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; 429 int ret, i; 430 431 if (chan->trigger_mask == 0) { 432 dev_err(chip->dev, "Channel doesn't have a trigger mask\n"); 433 return -EINVAL; 434 } 435 436 ret = regmap_set_bits(chip->regmap, chip->base + chan->trigger_addr, 437 chan->trigger_mask); 438 if (ret < 0) { 439 dev_err(chip->dev, 440 "Failed to apply trigger for channel '%s' ret=%d\n", 441 iio_chan->extend_name, ret); 442 return ret; 443 } 444 445 ret = rradc_enable_continuous_mode(chip); 446 if (ret < 0) { 447 dev_err(chip->dev, "Failed to switch to continuous mode\n"); 448 goto disable_trigger; 449 } 450 451 /* 452 * The wait/sleep values were found through trial and error, 453 * this is mostly for the battery ID channel which takes some 454 * time to settle. 455 */ 456 for (i = 0; i < 5; i++) { 457 if (rradc_is_ready(chip, chan_address)) 458 break; 459 usleep_range(50000, 50000 + 500); 460 } 461 462 if (i == 5) { 463 dev_err(chip->dev, "Channel '%s' is not ready\n", 464 iio_chan->extend_name); 465 ret = -ETIMEDOUT; 466 } 467 468 rradc_disable_continuous_mode(chip); 469 470 disable_trigger: 471 regmap_clear_bits(chip->regmap, chip->base + chan->trigger_addr, 472 chan->trigger_mask); 473 474 return ret; 475 } 476 477 static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip, 478 enum rradc_channel_id chan_address, 479 u16 *data) 480 { 481 int ret; 482 483 ret = regmap_set_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, 484 RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); 485 if (ret < 0) { 486 dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret); 487 return ret; 488 } 489 490 ret = regmap_set_bits(chip->regmap, 491 chip->base + RR_ADC_BATT_ID_TRIGGER, 492 RR_ADC_TRIGGER_CTL); 493 if (ret < 0) { 494 dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret); 495 goto out_disable_batt_id; 496 } 497 498 ret = rradc_read_status_in_cont_mode(chip, chan_address); 499 500 /* Reset registers back to default values */ 501 regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER, 502 RR_ADC_TRIGGER_CTL); 503 504 out_disable_batt_id: 505 regmap_clear_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL, 506 RR_ADC_BATT_ID_CTRL_CHANNEL_CONV); 507 508 return ret; 509 } 510 511 static int rradc_do_conversion(struct rradc_chip *chip, 512 enum rradc_channel_id chan_address, u16 *data) 513 { 514 const struct rradc_channel *chan = &rradc_chans[chan_address]; 515 const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address]; 516 int ret; 517 __le16 buf[3]; 518 519 mutex_lock(&chip->conversion_lock); 520 521 switch (chan_address) { 522 case RR_ADC_BATT_ID: 523 ret = rradc_prepare_batt_id_conversion(chip, chan_address, data); 524 if (ret < 0) { 525 dev_err(chip->dev, "Battery ID conversion failed:%d\n", 526 ret); 527 goto unlock_out; 528 } 529 break; 530 531 case RR_ADC_USBIN_V: 532 case RR_ADC_DIE_TEMP: 533 ret = rradc_read_status_in_cont_mode(chip, chan_address); 534 if (ret < 0) { 535 dev_err(chip->dev, 536 "Error reading in continuous mode:%d\n", ret); 537 goto unlock_out; 538 } 539 break; 540 default: 541 if (!rradc_is_ready(chip, chan_address)) { 542 /* 543 * Usually this means the channel isn't attached, for example 544 * the in_voltage_usbin_v_input channel will not be ready if 545 * no USB cable is attached 546 */ 547 dev_dbg(chip->dev, "channel '%s' is not ready\n", 548 iio_chan->extend_name); 549 ret = -ENODATA; 550 goto unlock_out; 551 } 552 break; 553 } 554 555 ret = rradc_read(chip, chan->lsb, buf, chan->size); 556 if (ret) { 557 dev_err(chip->dev, "read data failed\n"); 558 goto unlock_out; 559 } 560 561 /* 562 * For the battery ID we read the register for every ID ADC and then 563 * see which one is actually connected. 564 */ 565 if (chan_address == RR_ADC_BATT_ID) { 566 u16 batt_id_150 = le16_to_cpu(buf[2]); 567 u16 batt_id_15 = le16_to_cpu(buf[1]); 568 u16 batt_id_5 = le16_to_cpu(buf[0]); 569 570 if (!batt_id_150 && !batt_id_15 && !batt_id_5) { 571 dev_err(chip->dev, 572 "Invalid batt_id values with all zeros\n"); 573 ret = -EINVAL; 574 goto unlock_out; 575 } 576 577 if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) { 578 *data = batt_id_150; 579 chip->batt_id_data = 150; 580 } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) { 581 *data = batt_id_15; 582 chip->batt_id_data = 15; 583 } else { 584 *data = batt_id_5; 585 chip->batt_id_data = 5; 586 } 587 } else { 588 /* 589 * All of the other channels are either 1 or 2 bytes. 590 * We can rely on the second byte being 0 for 1-byte channels. 591 */ 592 *data = le16_to_cpu(buf[0]); 593 } 594 595 unlock_out: 596 mutex_unlock(&chip->conversion_lock); 597 598 return ret; 599 } 600 601 static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val, 602 int *val2) 603 { 604 int64_t fab_offset, fab_slope; 605 int ret; 606 607 ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); 608 if (ret < 0) { 609 dev_err(chip->dev, "Unable to get fab id coefficients\n"); 610 return -EINVAL; 611 } 612 613 switch (chan_address) { 614 case RR_ADC_SKIN_TEMP: 615 *val = MILLI; 616 *val2 = RR_ADC_BATT_THERM_LSB_K; 617 return IIO_VAL_FRACTIONAL; 618 case RR_ADC_USBIN_I: 619 *val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL * 620 RR_ADC_FS_VOLTAGE_MV; 621 *val2 = RR_ADC_CHAN_MSB; 622 return IIO_VAL_FRACTIONAL; 623 case RR_ADC_DCIN_I: 624 *val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV; 625 *val2 = RR_ADC_CHAN_MSB; 626 return IIO_VAL_FRACTIONAL; 627 case RR_ADC_USBIN_V: 628 case RR_ADC_DCIN_V: 629 *val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI; 630 *val2 = RR_ADC_CHAN_MSB; 631 return IIO_VAL_FRACTIONAL; 632 case RR_ADC_GPIO: 633 *val = RR_ADC_GPIO_FS_RANGE; 634 *val2 = RR_ADC_CHAN_MSB; 635 return IIO_VAL_FRACTIONAL; 636 case RR_ADC_CHG_TEMP: 637 /* 638 * We divide val2 by MILLI instead of multiplying val 639 * to avoid an integer overflow. 640 */ 641 *val = -RR_ADC_TEMP_FS_VOLTAGE_NUM; 642 *val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * 643 fab_slope, 644 MILLI); 645 646 return IIO_VAL_FRACTIONAL; 647 case RR_ADC_DIE_TEMP: 648 *val = RR_ADC_TEMP_FS_VOLTAGE_NUM; 649 *val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * 650 RR_ADC_DIE_TEMP_SLOPE; 651 652 return IIO_VAL_FRACTIONAL; 653 default: 654 return -EINVAL; 655 } 656 } 657 658 static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val) 659 { 660 int64_t fab_offset, fab_slope; 661 int64_t offset1, offset2; 662 int ret; 663 664 switch (chan_address) { 665 case RR_ADC_SKIN_TEMP: 666 /* 667 * Offset from kelvin to degC, divided by the 668 * scale factor (250). We lose some precision here. 669 * 273150 / 250 = 1092.6 670 */ 671 *val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS, 672 (MILLI / RR_ADC_BATT_THERM_LSB_K)); 673 return IIO_VAL_INT; 674 case RR_ADC_CHG_TEMP: 675 ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope); 676 if (ret < 0) { 677 dev_err(chip->dev, 678 "Unable to get fab id coefficients\n"); 679 return -EINVAL; 680 } 681 offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN * 682 RR_ADC_CHAN_MSB); 683 offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL; 684 offset1 = div64_s64(offset1, 685 (int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM)); 686 687 offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * 688 RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * 689 (int64_t)fab_slope; 690 offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2; 691 offset2 = div64_s64( 692 offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM)); 693 694 /* 695 * The -1 is to compensate for lost precision. 696 * It should actually be -0.7906976744186046. 697 * This works out to every value being off 698 * by about +0.091 degrees C after applying offset and scale. 699 */ 700 *val = (int)(offset1 - offset2 - 1); 701 return IIO_VAL_INT; 702 case RR_ADC_DIE_TEMP: 703 offset1 = -RR_ADC_DIE_TEMP_OFFSET * 704 (int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN * 705 (int64_t)RR_ADC_CHAN_MSB; 706 offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM); 707 708 offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC * 709 RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB * 710 RR_ADC_DIE_TEMP_SLOPE; 711 offset2 = div64_s64(offset2, 712 ((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM)); 713 714 /* 715 * The result is -339, it should be -338.69789, this results 716 * in the calculated die temp being off by 717 * -0.004 - -0.0175 degrees C 718 */ 719 *val = (int)(offset1 - offset2); 720 return IIO_VAL_INT; 721 default: 722 break; 723 } 724 return -EINVAL; 725 } 726 727 static int rradc_read_raw(struct iio_dev *indio_dev, 728 struct iio_chan_spec const *chan_spec, int *val, 729 int *val2, long mask) 730 { 731 struct rradc_chip *chip = iio_priv(indio_dev); 732 const struct rradc_channel *chan; 733 int ret; 734 u16 adc_code; 735 736 if (chan_spec->address >= RR_ADC_CHAN_MAX) { 737 dev_err(chip->dev, "Invalid channel index:%lu\n", 738 chan_spec->address); 739 return -EINVAL; 740 } 741 742 switch (mask) { 743 case IIO_CHAN_INFO_SCALE: 744 return rradc_read_scale(chip, chan_spec->address, val, val2); 745 case IIO_CHAN_INFO_OFFSET: 746 return rradc_read_offset(chip, chan_spec->address, val); 747 case IIO_CHAN_INFO_RAW: 748 ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); 749 if (ret < 0) 750 return ret; 751 752 *val = adc_code; 753 return IIO_VAL_INT; 754 case IIO_CHAN_INFO_PROCESSED: 755 chan = &rradc_chans[chan_spec->address]; 756 if (!chan->scale_fn) 757 return -EINVAL; 758 ret = rradc_do_conversion(chip, chan_spec->address, &adc_code); 759 if (ret < 0) 760 return ret; 761 762 *val = chan->scale_fn(chip, adc_code, val); 763 return IIO_VAL_INT; 764 default: 765 return -EINVAL; 766 } 767 } 768 769 static int rradc_read_label(struct iio_dev *indio_dev, 770 struct iio_chan_spec const *chan, char *label) 771 { 772 return snprintf(label, PAGE_SIZE, "%s\n", 773 rradc_chans[chan->address].label); 774 } 775 776 static const struct iio_info rradc_info = { 777 .read_raw = rradc_read_raw, 778 .read_label = rradc_read_label, 779 }; 780 781 static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = { 782 { 783 .label = "batt_id", 784 .scale_fn = rradc_post_process_batt_id, 785 .lsb = RR_ADC_BATT_ID_5_LSB, 786 .status = RR_ADC_BATT_ID_STS, 787 .size = 6, 788 .trigger_addr = RR_ADC_BATT_ID_TRIGGER, 789 .trigger_mask = BIT(0), 790 }, { 791 .label = "batt", 792 .lsb = RR_ADC_BATT_THERM_LSB, 793 .status = RR_ADC_BATT_THERM_STS, 794 .size = 2, 795 .trigger_addr = RR_ADC_BATT_THERM_TRIGGER, 796 }, { 797 .label = "pmi8998_skin", 798 .lsb = RR_ADC_SKIN_TEMP_LSB, 799 .status = RR_ADC_AUX_THERM_STS, 800 .size = 2, 801 .trigger_addr = RR_ADC_AUX_THERM_TRIGGER, 802 }, { 803 .label = "usbin_i", 804 .lsb = RR_ADC_USB_IN_I_LSB, 805 .status = RR_ADC_USB_IN_I_STS, 806 .size = 2, 807 .trigger_addr = RR_ADC_USB_IN_I_TRIGGER, 808 }, { 809 .label = "usbin_v", 810 .lsb = RR_ADC_USB_IN_V_LSB, 811 .status = RR_ADC_USB_IN_V_STS, 812 .size = 2, 813 .trigger_addr = RR_ADC_USB_IN_V_TRIGGER, 814 .trigger_mask = BIT(7), 815 }, { 816 .label = "dcin_i", 817 .lsb = RR_ADC_DC_IN_I_LSB, 818 .status = RR_ADC_DC_IN_I_STS, 819 .size = 2, 820 .trigger_addr = RR_ADC_DC_IN_I_TRIGGER, 821 }, { 822 .label = "dcin_v", 823 .lsb = RR_ADC_DC_IN_V_LSB, 824 .status = RR_ADC_DC_IN_V_STS, 825 .size = 2, 826 .trigger_addr = RR_ADC_DC_IN_V_TRIGGER, 827 }, { 828 .label = "pmi8998_die", 829 .lsb = RR_ADC_PMI_DIE_TEMP_LSB, 830 .status = RR_ADC_PMI_DIE_TEMP_STS, 831 .size = 2, 832 .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER, 833 .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE, 834 }, { 835 .label = "chg", 836 .lsb = RR_ADC_CHARGER_TEMP_LSB, 837 .status = RR_ADC_CHARGER_TEMP_STS, 838 .size = 2, 839 .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER, 840 }, { 841 .label = "gpio", 842 .lsb = RR_ADC_GPIO_LSB, 843 .status = RR_ADC_GPIO_STS, 844 .size = 2, 845 .trigger_addr = RR_ADC_GPIO_TRIGGER, 846 }, 847 }; 848 849 static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = { 850 { 851 .type = IIO_RESISTANCE, 852 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 853 .address = RR_ADC_BATT_ID, 854 .channel = 0, 855 .indexed = 1, 856 }, { 857 .type = IIO_TEMP, 858 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 859 .address = RR_ADC_BATT_THERM, 860 .channel = 0, 861 .indexed = 1, 862 }, { 863 .type = IIO_TEMP, 864 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 865 BIT(IIO_CHAN_INFO_SCALE) | 866 BIT(IIO_CHAN_INFO_OFFSET), 867 .address = RR_ADC_SKIN_TEMP, 868 .channel = 1, 869 .indexed = 1, 870 }, { 871 .type = IIO_CURRENT, 872 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 873 BIT(IIO_CHAN_INFO_SCALE), 874 .address = RR_ADC_USBIN_I, 875 .channel = 0, 876 .indexed = 1, 877 }, { 878 .type = IIO_VOLTAGE, 879 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 880 BIT(IIO_CHAN_INFO_SCALE), 881 .address = RR_ADC_USBIN_V, 882 .channel = 0, 883 .indexed = 1, 884 }, { 885 .type = IIO_CURRENT, 886 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 887 BIT(IIO_CHAN_INFO_SCALE), 888 .address = RR_ADC_DCIN_I, 889 .channel = 1, 890 .indexed = 1, 891 }, { 892 .type = IIO_VOLTAGE, 893 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 894 BIT(IIO_CHAN_INFO_SCALE), 895 .address = RR_ADC_DCIN_V, 896 .channel = 1, 897 .indexed = 1, 898 }, { 899 .type = IIO_TEMP, 900 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 901 BIT(IIO_CHAN_INFO_SCALE) | 902 BIT(IIO_CHAN_INFO_OFFSET), 903 .address = RR_ADC_DIE_TEMP, 904 .channel = 2, 905 .indexed = 1, 906 }, { 907 .type = IIO_TEMP, 908 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 909 BIT(IIO_CHAN_INFO_OFFSET) | 910 BIT(IIO_CHAN_INFO_SCALE), 911 .address = RR_ADC_CHG_TEMP, 912 .channel = 3, 913 .indexed = 1, 914 }, { 915 .type = IIO_VOLTAGE, 916 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) | 917 BIT(IIO_CHAN_INFO_SCALE), 918 .address = RR_ADC_GPIO, 919 .channel = 2, 920 .indexed = 1, 921 }, 922 }; 923 924 static int rradc_probe(struct platform_device *pdev) 925 { 926 struct device *dev = &pdev->dev; 927 struct iio_dev *indio_dev; 928 struct rradc_chip *chip; 929 int ret, i, batt_id_delay; 930 931 indio_dev = devm_iio_device_alloc(dev, sizeof(*chip)); 932 if (!indio_dev) 933 return -ENOMEM; 934 935 chip = iio_priv(indio_dev); 936 chip->regmap = dev_get_regmap(pdev->dev.parent, NULL); 937 if (!chip->regmap) { 938 dev_err(dev, "Couldn't get parent's regmap\n"); 939 return -EINVAL; 940 } 941 942 chip->dev = dev; 943 mutex_init(&chip->conversion_lock); 944 945 ret = device_property_read_u32(dev, "reg", &chip->base); 946 if (ret < 0) { 947 dev_err(chip->dev, "Couldn't find reg address, ret = %d\n", 948 ret); 949 return ret; 950 } 951 952 batt_id_delay = -1; 953 ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms", 954 &batt_id_delay); 955 if (!ret) { 956 for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) { 957 if (batt_id_delay == batt_id_delays[i]) 958 break; 959 } 960 if (i == RRADC_BATT_ID_DELAY_MAX) 961 batt_id_delay = -1; 962 } 963 964 if (batt_id_delay >= 0) { 965 batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay); 966 ret = regmap_set_bits(chip->regmap, 967 chip->base + RR_ADC_BATT_ID_CFG, 968 batt_id_delay); 969 if (ret < 0) { 970 dev_err(chip->dev, 971 "BATT_ID settling time config failed:%d\n", 972 ret); 973 } 974 } 975 976 /* Get the PMIC revision, we need it to handle some varying coefficients */ 977 chip->pmic = qcom_pmic_get(chip->dev); 978 if (IS_ERR(chip->pmic)) { 979 dev_err(chip->dev, "Unable to get reference to PMIC device\n"); 980 return PTR_ERR(chip->pmic); 981 } 982 983 switch (chip->pmic->subtype) { 984 case PMI8998_SUBTYPE: 985 indio_dev->name = "pmi8998-rradc"; 986 break; 987 case PM660_SUBTYPE: 988 indio_dev->name = "pm660-rradc"; 989 break; 990 default: 991 indio_dev->name = DRIVER_NAME; 992 break; 993 } 994 indio_dev->modes = INDIO_DIRECT_MODE; 995 indio_dev->info = &rradc_info; 996 indio_dev->channels = rradc_iio_chans; 997 indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans); 998 999 return devm_iio_device_register(dev, indio_dev); 1000 } 1001 1002 static const struct of_device_id rradc_match_table[] = { 1003 { .compatible = "qcom,pm660-rradc" }, 1004 { .compatible = "qcom,pmi8998-rradc" }, 1005 { } 1006 }; 1007 MODULE_DEVICE_TABLE(of, rradc_match_table); 1008 1009 static struct platform_driver rradc_driver = { 1010 .driver = { 1011 .name = DRIVER_NAME, 1012 .of_match_table = rradc_match_table, 1013 }, 1014 .probe = rradc_probe, 1015 }; 1016 module_platform_driver(rradc_driver); 1017 1018 MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver"); 1019 MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>"); 1020 MODULE_LICENSE("GPL"); 1021