Lines Matching full:i2c
3 * i2c-xiic.c
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
36 #define DRIVER_NAME "xiic-i2c"
58 * struct xiic_i2c - Internal representation of the XIIC I2C bus
77 * @input_clk: Input clock to I2C controller
78 * @i2c_clk: I2C SCL frequency
114 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
129 /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
156 * setting i2c clock frequency for the line.
245 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
246 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
248 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
249 static void __xiic_start_xfer(struct xiic_i2c *i2c);
253 struct xiic_i2c *i2c = dev_get_drvdata(dev);
255 clk_disable(i2c->clk);
262 struct xiic_i2c *i2c = dev_get_drvdata(dev);
265 ret = clk_enable(i2c->clk);
282 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
284 if (i2c->endianness == LITTLE)
285 iowrite8(value, i2c->base + reg);
287 iowrite8(value, i2c->base + reg + 3);
290 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
294 if (i2c->endianness == LITTLE)
295 ret = ioread8(i2c->base + reg);
297 ret = ioread8(i2c->base + reg + 3);
301 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
303 if (i2c->endianness == LITTLE)
304 iowrite16(value, i2c->base + reg);
306 iowrite16be(value, i2c->base + reg + 2);
309 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
311 if (i2c->endianness == LITTLE)
312 iowrite32(value, i2c->base + reg);
314 iowrite32be(value, i2c->base + reg);
317 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
321 if (i2c->endianness == LITTLE)
322 ret = ioread32(i2c->base + reg);
324 ret = ioread32be(i2c->base + reg);
328 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
330 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
332 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
335 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
337 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
339 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
342 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
344 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
346 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
349 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
351 xiic_irq_clr(i2c, mask);
352 xiic_irq_en(i2c, mask);
355 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
361 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
363 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
364 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
366 dev_err(i2c->dev, "Failed to clear rx fifo\n");
374 static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
380 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
382 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) {
384 dev_err(i2c->dev, "Timeout waiting at Tx empty\n");
394 * @i2c: Pointer to the xiic device structure
398 * AXI I2C PG and NXP I2C Spec.
404 static int xiic_setclk(struct xiic_i2c *i2c)
410 if (!i2c->atomic)
411 dev_dbg(i2c->adap.dev.parent,
412 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
413 __func__, i2c->input_clk, i2c->i2c_clk);
416 if (!i2c->i2c_clk || !i2c->input_clk)
419 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
421 switch (i2c->i2c_clk) {
432 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
439 * period to get the number of clock cycles required. Refer Xilinx AXI I2C
440 * PG document and I2C specification for further details.
444 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
448 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
451 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
455 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
459 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
463 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
467 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
471 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
474 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
479 static int xiic_reinit(struct xiic_i2c *i2c)
483 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
485 ret = xiic_setclk(i2c);
490 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
493 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
496 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
499 ret = xiic_clear_rx_fifo(i2c);
504 if (!i2c->atomic)
505 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
507 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
512 static void xiic_deinit(struct xiic_i2c *i2c)
516 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
519 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
520 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
523 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
531 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN;
534 i2c->smbus_block_read = true;
537 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
539 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len;
550 i2c->rx_msg->len = rxmsg_len + 1;
559 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN;
566 i2c->rx_msg->len = rxmsg_len + 1;
568 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
574 i2c->tx_msg->len = 3;
575 i2c->smbus_block_read = false;
576 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n");
579 static void xiic_read_rx(struct xiic_i2c *i2c)
585 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
587 if (!i2c->atomic)
588 dev_dbg(i2c->adap.dev.parent,
590 __func__, bytes_in_fifo, xiic_rx_space(i2c),
591 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
592 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
594 if (bytes_in_fifo > xiic_rx_space(i2c))
595 bytes_in_fifo = xiic_rx_space(i2c);
599 if (!i2c->dynamic) {
600 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo;
603 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) {
604 xiic_smbus_block_read_setup(i2c);
615 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
616 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
622 if (i2c->nmsgs == 1) {
623 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
624 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
629 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
630 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
637 i2c->rx_msg->buf[i2c->rx_pos++] =
638 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
641 if (i2c->dynamic) {
645 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH);
647 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
651 static bool xiic_error_check(struct xiic_i2c *i2c)
656 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
657 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
663 xiic_reinit(i2c);
665 if (i2c->tx_msg || i2c->rx_msg)
666 i2c->atomic_xfer_state = STATE_ERROR;
671 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
674 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
677 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
679 u8 fifo_space = xiic_tx_fifo_space(i2c);
680 int len = xiic_tx_space(i2c);
684 if (!i2c->atomic)
685 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
689 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
691 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
693 if (i2c->dynamic) {
700 status = xiic_wait_tx_empty(i2c);
705 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
706 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
709 if (!i2c->atomic)
710 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
712 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
714 if (i2c->atomic && xiic_error_check(i2c))
719 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code)
721 i2c->tx_msg = NULL;
722 i2c->rx_msg = NULL;
723 i2c->nmsgs = 0;
724 i2c->state = code;
725 complete(&i2c->completion);
730 struct xiic_i2c *i2c = dev_id;
743 mutex_lock(&i2c->lock);
744 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
745 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
748 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
750 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
751 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
752 i2c->tx_msg, i2c->nmsgs);
753 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n",
754 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
755 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
767 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
773 ret = xiic_reinit(i2c);
775 dev_dbg(i2c->adap.dev.parent, "reinit failed\n");
777 if (i2c->rx_msg) {
781 if (i2c->tx_msg) {
792 if (!i2c->rx_msg) {
793 dev_dbg(i2c->adap.dev.parent,
795 xiic_clear_rx_fifo(i2c);
799 xiic_read_rx(i2c);
800 if (xiic_rx_space(i2c) == 0) {
802 i2c->rx_msg = NULL;
807 dev_dbg(i2c->adap.dev.parent,
809 __func__, i2c->nmsgs);
815 if (i2c->nmsgs > 1) {
816 i2c->nmsgs--;
817 i2c->tx_msg++;
818 dev_dbg(i2c->adap.dev.parent,
830 if (!i2c->tx_msg) {
831 dev_dbg(i2c->adap.dev.parent,
836 if (xiic_tx_space(i2c)) {
837 xiic_fill_tx_fifo(i2c);
840 dev_dbg(i2c->adap.dev.parent,
842 __func__, i2c->nmsgs);
846 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) {
847 i2c->nmsgs--;
848 i2c->tx_msg++;
851 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
853 dev_dbg(i2c->adap.dev.parent,
865 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
867 if (i2c->tx_msg && i2c->smbus_block_read) {
868 i2c->smbus_block_read = false;
870 i2c->tx_msg->len = 1;
873 if (!i2c->tx_msg)
878 if (i2c->nmsgs == 1 && !i2c->rx_msg &&
879 xiic_tx_space(i2c) == 0)
886 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
888 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
890 __xiic_start_xfer(i2c);
892 xiic_wakeup(i2c, wakeup_code);
896 mutex_unlock(&i2c->lock);
900 static int xiic_bus_busy(struct xiic_i2c *i2c)
902 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
907 static int xiic_wait_not_busy(struct xiic_i2c *i2c)
916 err = xiic_bus_busy(i2c);
918 if (i2c->atomic)
922 err = xiic_bus_busy(i2c);
928 static void xiic_recv_atomic(struct xiic_i2c *i2c)
930 while (xiic_rx_space(i2c)) {
931 if (xiic_getreg32(i2c, XIIC_IISR_OFFSET) & XIIC_INTR_RX_FULL_MASK) {
932 xiic_read_rx(i2c);
935 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
938 if (xiic_error_check(i2c))
942 i2c->rx_msg = NULL;
943 xiic_irq_clr_en(i2c, XIIC_INTR_TX_ERROR_MASK);
946 if (i2c->nmsgs > 1) {
947 i2c->nmsgs--;
948 i2c->tx_msg++;
949 __xiic_start_xfer(i2c);
953 static void xiic_start_recv(struct xiic_i2c *i2c)
957 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
959 if (!i2c->atomic)
960 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
961 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
962 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
965 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK);
967 if (i2c->dynamic) {
972 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
988 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
991 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
996 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
999 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
1001 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
1009 if (i2c->prev_msg_tx) {
1012 status = xiic_wait_tx_empty(i2c);
1017 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1027 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) {
1039 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1044 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
1047 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
1051 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
1056 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1060 if (!i2c->atomic)
1061 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
1062 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1063 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1066 if (i2c->nmsgs == 1)
1068 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
1071 i2c->tx_pos = msg->len;
1073 i2c->prev_msg_tx = false;
1076 if (!i2c->atomic)
1077 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
1079 xiic_recv_atomic(i2c);
1082 static void xiic_send_rem_atomic(struct xiic_i2c *i2c)
1084 while (xiic_tx_space(i2c)) {
1085 if (xiic_tx_fifo_space(i2c)) {
1088 data = i2c->tx_msg->buf[i2c->tx_pos];
1089 i2c->tx_pos++;
1090 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
1092 if (i2c->dynamic) {
1099 status = xiic_wait_tx_empty(i2c);
1104 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1105 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
1109 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1111 if (xiic_error_check(i2c))
1115 if (i2c->nmsgs > 1) {
1116 i2c->nmsgs--;
1117 i2c->tx_msg++;
1118 __xiic_start_xfer(i2c);
1120 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
1124 static void xiic_start_send(struct xiic_i2c *i2c)
1128 struct i2c_msg *msg = i2c->tx_msg;
1130 if (!i2c->atomic) {
1131 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
1133 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
1134 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1135 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1138 if (i2c->dynamic) {
1143 if (i2c->nmsgs == 1 && msg->len == 0)
1147 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1150 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1153 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ?
1156 xiic_fill_tx_fifo(i2c);
1164 if (i2c->prev_msg_tx) {
1167 status = xiic_wait_tx_empty(i2c);
1172 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1175 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1183 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1186 xiic_fill_tx_fifo(i2c);
1190 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1191 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
1197 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1202 i2c->prev_msg_tx = true;
1204 if (i2c->atomic && !i2c->atomic_xfer_state)
1205 xiic_send_rem_atomic(i2c);
1208 static void __xiic_start_xfer(struct xiic_i2c *i2c)
1210 int fifo_space = xiic_tx_fifo_space(i2c);
1212 if (!i2c->atomic)
1213 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
1214 __func__, i2c->tx_msg, fifo_space);
1216 if (!i2c->tx_msg)
1219 if (i2c->atomic && xiic_error_check(i2c))
1222 i2c->rx_pos = 0;
1223 i2c->tx_pos = 0;
1224 i2c->state = STATE_START;
1225 if (i2c->tx_msg->flags & I2C_M_RD) {
1227 xiic_start_recv(i2c);
1229 xiic_start_send(i2c);
1233 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
1238 if (i2c->atomic)
1239 spin_lock(&i2c->atomic_lock);
1241 mutex_lock(&i2c->lock);
1243 if (i2c->tx_msg || i2c->rx_msg) {
1244 dev_err(i2c->adap.dev.parent,
1250 i2c->atomic_xfer_state = STATE_DONE;
1254 * should ignore it, since bus will never be released and i2c will be
1257 if (!i2c->singlemaster) {
1258 ret = xiic_wait_not_busy(i2c);
1265 dev_warn(i2c->adap.dev.parent, "I2C bus busy timeout, reinitializing\n");
1266 ret = xiic_reinit(i2c);
1269 ret = xiic_wait_not_busy(i2c);
1275 i2c->tx_msg = msgs;
1276 i2c->rx_msg = NULL;
1277 i2c->nmsgs = num;
1279 if (!i2c->atomic)
1280 init_completion(&i2c->completion);
1283 i2c->dynamic = true;
1286 i2c->prev_msg_tx = false;
1297 for (count = 0; count < i2c->nmsgs; count++) {
1298 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) &&
1299 (i2c->tx_msg[count].flags & I2C_M_RD);
1300 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) &&
1301 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC);
1302 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN);
1305 i2c->dynamic = false;
1310 ret = xiic_reinit(i2c);
1312 __xiic_start_xfer(i2c);
1315 if (i2c->atomic)
1316 spin_unlock(&i2c->atomic_lock);
1318 mutex_unlock(&i2c->lock);
1325 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1329 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
1331 err = pm_runtime_resume_and_get(i2c->dev);
1335 err = xiic_start_xfer(i2c, msgs, num);
1339 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT);
1340 mutex_lock(&i2c->lock);
1342 i2c->tx_msg = NULL;
1343 i2c->rx_msg = NULL;
1344 i2c->nmsgs = 0;
1347 err = (i2c->state == STATE_DONE) ? num : -EIO;
1349 mutex_unlock(&i2c->lock);
1352 pm_runtime_mark_last_busy(i2c->dev);
1353 pm_runtime_put_autosuspend(i2c->dev);
1359 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1363 err = xiic_i2c_runtime_resume(i2c->dev);
1367 i2c->atomic = true;
1368 err = xiic_start_xfer(i2c, msgs, num);
1372 err = readl_poll_timeout_atomic(i2c->base + XIIC_SR_REG_OFFSET,
1379 spin_lock(&i2c->atomic_lock);
1380 if (err || i2c->state) {
1381 i2c->tx_msg = NULL;
1382 i2c->rx_msg = NULL;
1383 i2c->nmsgs = 0;
1386 err = (i2c->atomic_xfer_state == STATE_DONE) ? num : -EIO;
1387 spin_unlock(&i2c->atomic_lock);
1389 i2c->atomic = false;
1390 xiic_i2c_runtime_suspend(i2c->dev);
1427 struct xiic_i2c *i2c;
1435 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1436 if (!i2c)
1443 i2c->quirks = data->quirks;
1446 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1447 if (IS_ERR(i2c->base))
1448 return PTR_ERR(i2c->base);
1457 platform_set_drvdata(pdev, i2c);
1458 i2c->adap = xiic_adapter;
1459 i2c_set_adapdata(&i2c->adap, i2c);
1460 i2c->adap.dev.parent = &pdev->dev;
1461 i2c->adap.dev.of_node = pdev->dev.of_node;
1462 snprintf(i2c->adap.name, sizeof(i2c->adap.name),
1465 mutex_init(&i2c->lock);
1466 spin_lock_init(&i2c->atomic_lock);
1468 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1469 if (IS_ERR(i2c->clk))
1470 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
1473 i2c->dev = &pdev->dev;
1474 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
1475 pm_runtime_use_autosuspend(i2c->dev);
1476 pm_runtime_set_active(i2c->dev);
1477 pm_runtime_enable(i2c->dev);
1480 i2c->input_clk = clk_get_rate(i2c->clk);
1482 &i2c->i2c_clk);
1484 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
1485 i2c->i2c_clk = 0;
1489 pdev->name, i2c);
1496 i2c->singlemaster =
1504 i2c->endianness = LITTLE;
1505 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
1507 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
1509 i2c->endianness = BIG;
1511 ret = xiic_reinit(i2c);
1517 /* add i2c adapter to i2c tree */
1518 ret = i2c_add_adapter(&i2c->adap);
1520 xiic_deinit(i2c);
1527 i2c_new_client_device(&i2c->adap, pdata->devices + i);
1531 (unsigned long)res->start, irq, i2c->i2c_clk);
1544 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
1548 i2c_del_adapter(&i2c->adap);
1550 ret = pm_runtime_get_sync(i2c->dev);
1556 xiic_deinit(i2c);
1558 pm_runtime_put_sync(i2c->dev);
1583 MODULE_DESCRIPTION("Xilinx I2C bus driver");