Lines Matching full:as
20 3:0 minor_revision as u8, "Minor revision of the chip";
21 7:4 major_revision as u8, "Major revision of the chip";
22 8:8 architecture_1 as u8, "MSB of the architecture";
23 23:20 implementation as u8, "Implementation version of the architecture";
24 28:24 architecture_0 as u8, "Lower bits of the architecture";
39 ((arch as u32) << Self::IMPLEMENTATION.len()) | u32::from(self.implementation()) in chipset()
49 31:16 frts_err_code as u16;
58 31:0 adr_39_08 as u32;
62 23:0 adr_63_40 as u32;
66 3:0 lower_scale as u8;
67 9:4 lower_mag as u8;
68 30:30 ecc_mode_enabled as bool;
75 * kernel::sizes::SZ_1M as u64; in usable_fb_size()
87 31:4 lo_val as u32, "Bits 12..40 of the lower (inclusive) bound of the WPR2 region";
98 31:4 hi_val as u32, "Bits 12..40 of the higher (exclusive) bound of the WPR2 region";
123 0:0 read_protection_level0 as bool, "Set after FWSEC lowers its protection level";
128 31:0 value as u32;
133 "Scratch group 05 register 0 used as GFW boot progress indicator" {
134 7:0 progress as u8, "Progress of GFW boot (0xff means completed)";
146 31:0 value as u32;
151 "Scratch group 42 register used as framebuffer size" {
152 31:0 value as u32, "Usable framebuffer size, in megabytes";
159 u64::from(self.value()) * kernel::sizes::SZ_1M as u64 in usable_fb_size()
166 3:3 status_valid as bool, "Set if the `addr` field is valid";
167 31:8 addr as u32, "VGA workspace base address divided by 0x10000";
184 15:0 data as u16;
188 15:0 data as u16;
192 15:0 data as u16;
198 4:4 halt as bool;
199 6:6 swgen0 as bool;
203 31:0 value as u32;
207 31:0 value as u32;
211 31:0 value as u32;
215 10:10 riscv as bool;
216 12:12 mem_scrubbing as bool, "Set to 0 after memory scrubbing is completed";
217 31:31 reset_ready as bool, "Signal indicating that reset is completed (GA102+)";
228 1:1 startcpu as bool;
229 4:4 halted as bool;
230 6:6 alias_en as bool;
234 31:0 value as u32;
238 0:0 require_ctx as bool;
239 1:1 dmem_scrubbing as bool;
240 2:2 imem_scrubbing as bool;
241 6:3 dmaq_num as u8;
242 7:7 secure_stat as bool;
246 31:0 base as u32;
250 23:0 offs as u32;
254 0:0 full as bool;
255 1:1 idle as bool;
256 3:2 sec as u8;
257 4:4 imem as bool;
258 5:5 is_write as bool;
259 10:8 size as u8 ?=> DmaTrfCmdSize;
260 14:12 ctxdma as u8;
261 16:16 set_dmtag as u8;
265 31:0 offs as u32;
269 8:0 base as u16;
273 3:0 core_rev as u8 ?=> FalconCoreRev, "Core revision";
274 5:4 security_model as u8 ?=> FalconSecurityModel, "Security model";
275 7:6 core_rev_subversion as u8 ?=> FalconCoreRevSubversion, "Core revision subversion";
279 1:1 startcpu as bool;
282 // Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the falcon
285 0:0 reset as bool;
290 1:0 target as u8 ?=> FalconFbifTarget;
291 2:2 mem_type as bool => FalconFbifMemType;
295 7:7 allow_phys_no_ctx as bool;
299 7:0 algo as u8 ?=> FalconModSelAlgo;
303 7:0 ucode_id as u8;
307 31:0 value as u32;
312 31:0 value as u32;
318 0:0 valid as bool;
319 4:4 core_select as bool => PeregrineCoreSelect;
320 8:8 br_fetch as bool;
330 0:0 display_disabled as bool;
338 0:0 display_disabled as bool;