31 static void __vlv_punit_get(struct drm_i915_private *i915)  in __vlv_punit_get()  argument
45 	if (IS_VALLEYVIEW(i915)) {  in __vlv_punit_get()
46 		cpu_latency_qos_update_request(&i915->sb_qos, 0);  in __vlv_punit_get()
51 static void __vlv_punit_put(struct drm_i915_private *i915)  in __vlv_punit_put()  argument
53 	if (IS_VALLEYVIEW(i915))  in __vlv_punit_put()
54 		cpu_latency_qos_update_request(&i915->sb_qos,  in __vlv_punit_put()
60 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)  in vlv_iosf_sb_get()  argument
63 		__vlv_punit_get(i915);  in vlv_iosf_sb_get()
65 	mutex_lock(&i915->sb_lock);  in vlv_iosf_sb_get()
68 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)  in vlv_iosf_sb_put()  argument
70 	mutex_unlock(&i915->sb_lock);  in vlv_iosf_sb_put()
73 		__vlv_punit_put(i915);  in vlv_iosf_sb_put()
76 static int vlv_sideband_rw(struct drm_i915_private *i915,  in vlv_sideband_rw()  argument
80 	struct intel_uncore *uncore = &i915->uncore;  in vlv_sideband_rw()
84 	lockdep_assert_held(&i915->sb_lock);  in vlv_sideband_rw()
92 		drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",  in vlv_sideband_rw()
116 		drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",  in vlv_sideband_rw()
126 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)  in vlv_punit_read()  argument
130 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,  in vlv_punit_read()
136 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)  in vlv_punit_write()  argument
138 	return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,  in vlv_punit_write()
142 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)  in vlv_bunit_read()  argument
146 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,  in vlv_bunit_read()
152 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)  in vlv_bunit_write()  argument
154 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,  in vlv_bunit_write()
158 u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)  in vlv_nc_read()  argument
162 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,  in vlv_nc_read()
168 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)  in vlv_cck_read()  argument
172 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,  in vlv_cck_read()
178 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)  in vlv_cck_write()  argument
180 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,  in vlv_cck_write()
184 u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)  in vlv_ccu_read()  argument
188 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,  in vlv_ccu_read()
194 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)  in vlv_ccu_write()  argument
196 	vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,  in vlv_ccu_write()
200 static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)  in vlv_dpio_phy_iosf_port()  argument
206 	if (IS_CHERRYVIEW(i915))  in vlv_dpio_phy_iosf_port()
212 u32 vlv_dpio_read(struct drm_i915_private *i915, enum dpio_phy phy, int reg)  in vlv_dpio_read()  argument
214 	u32 port = vlv_dpio_phy_iosf_port(i915, phy);  in vlv_dpio_read()
217 	vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);  in vlv_dpio_read()
223 	drm_WARN(&i915->drm, val == 0xffffffff,  in vlv_dpio_read()
230 void vlv_dpio_write(struct drm_i915_private *i915,  in vlv_dpio_write()  argument
233 	u32 port = vlv_dpio_phy_iosf_port(i915, phy);  in vlv_dpio_write()
235 	vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);  in vlv_dpio_write()
238 u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)  in vlv_flisdsi_read()  argument
242 	vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,  in vlv_flisdsi_read()
247 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)  in vlv_flisdsi_write()  argument
249 	vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,  in vlv_flisdsi_write()