353 	enum plane_id plane_id;  in skl_crtc_can_enable_sagv()  local
365 	for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_crtc_can_enable_sagv()
367 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
387 	for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_crtc_can_enable_sagv()
389 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
405 	enum plane_id plane_id;  in tgl_crtc_can_enable_sagv()  local
410 	for_each_plane_id_on_crtc(crtc, plane_id) {  in tgl_crtc_can_enable_sagv()
412 			&crtc_state->wm.skl.optimal.planes[plane_id];  in tgl_crtc_can_enable_sagv()
796 			   const enum plane_id plane_id,  in skl_ddb_get_hw_plane_state()  argument
803 	if (plane_id == PLANE_CURSOR) {  in skl_ddb_get_hw_plane_state()
809 	val = intel_de_read(i915, PLANE_BUF_CFG(pipe, plane_id));  in skl_ddb_get_hw_plane_state()
815 	val = intel_de_read(i915, PLANE_NV12_BUF_CFG(pipe, plane_id));  in skl_ddb_get_hw_plane_state()
827 	enum plane_id plane_id;  in skl_pipe_ddb_get_hw_state()  local
834 	for_each_plane_id_on_crtc(crtc, plane_id)  in skl_pipe_ddb_get_hw_state()
836 					   plane_id,  in skl_pipe_ddb_get_hw_state()
837 					   &ddb[plane_id],  in skl_pipe_ddb_get_hw_state()
838 					   &ddb_y[plane_id]);  in skl_pipe_ddb_get_hw_state()
1385 	enum plane_id plane_id;  in skl_total_relative_data_rate()  local
1388 	for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_total_relative_data_rate()
1389 		if (plane_id == PLANE_CURSOR)  in skl_total_relative_data_rate()
1392 		data_rate += crtc_state->rel_data_rate[plane_id];  in skl_total_relative_data_rate()
1395 			data_rate += crtc_state->rel_data_rate_y[plane_id];  in skl_total_relative_data_rate()
1403 		   enum plane_id plane_id,  in skl_plane_wm_level()  argument
1406 	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];  in skl_plane_wm_level()
1416 		   enum plane_id plane_id)  in skl_plane_trans_wm()  argument
1418 	const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];  in skl_plane_trans_wm()
1518 	enum plane_id plane_id;  in skl_crtc_allocate_plane_ddb()  local
1549 		for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_crtc_allocate_plane_ddb()
1551 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1553 			if (plane_id == PLANE_CURSOR) {  in skl_crtc_allocate_plane_ddb()
1555 					&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1593 	for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_crtc_allocate_plane_ddb()
1595 			&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1597 			&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_crtc_allocate_plane_ddb()
1599 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1601 		if (plane_id == PLANE_CURSOR)  in skl_crtc_allocate_plane_ddb()
1605 		    crtc_state->nv12_planes & BIT(plane_id)) {  in skl_crtc_allocate_plane_ddb()
1607 					       crtc_state->rel_data_rate_y[plane_id]);  in skl_crtc_allocate_plane_ddb()
1609 					       crtc_state->rel_data_rate[plane_id]);  in skl_crtc_allocate_plane_ddb()
1612 					       crtc_state->rel_data_rate[plane_id]);  in skl_crtc_allocate_plane_ddb()
1624 		for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_crtc_allocate_plane_ddb()
1626 				&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1628 				&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_crtc_allocate_plane_ddb()
1630 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1633 			    crtc_state->nv12_planes & BIT(plane_id))  in skl_crtc_allocate_plane_ddb()
1652 	for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_crtc_allocate_plane_ddb()
1654 			&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_crtc_allocate_plane_ddb()
1656 			&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_crtc_allocate_plane_ddb()
1658 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1661 		    crtc_state->nv12_planes & BIT(plane_id)) {  in skl_crtc_allocate_plane_ddb()
2166 	enum plane_id plane_id = plane->id;  in skl_build_plane_wm()  local
2167 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in skl_build_plane_wm()
2196 	enum plane_id plane_id = plane->id;  in icl_build_plane_wm()  local
2197 	struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];  in icl_build_plane_wm()
2250 	enum plane_id plane_id;  in skl_max_wm0_lines()  local
2253 	for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_max_wm0_lines()
2254 		const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];  in skl_max_wm0_lines()
2311 		enum plane_id plane_id;  in skl_wm_check_vblank()  local
2313 		for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_wm_check_vblank()
2315 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_wm_check_vblank()
2330 		enum plane_id plane_id;  in skl_wm_check_vblank()  local
2332 		for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_wm_check_vblank()
2334 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_wm_check_vblank()
2452 		enum plane_id plane_id = plane->id;  in skl_ddb_add_affected_planes()  local
2454 		if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb[plane_id],  in skl_ddb_add_affected_planes()
2455 					&new_crtc_state->wm.skl.plane_ddb[plane_id]) &&  in skl_ddb_add_affected_planes()
2456 		    skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],  in skl_ddb_add_affected_planes()
2457 					&new_crtc_state->wm.skl.plane_ddb_y[plane_id]))  in skl_ddb_add_affected_planes()
2470 		new_crtc_state->update_planes |= BIT(plane_id);  in skl_ddb_add_affected_planes()
2628 			enum plane_id plane_id = plane->id;  in skl_print_wm_changes()  local
2631 			old = &old_crtc_state->wm.skl.plane_ddb[plane_id];  in skl_print_wm_changes()
2632 			new = &new_crtc_state->wm.skl.plane_ddb[plane_id];  in skl_print_wm_changes()
2645 			enum plane_id plane_id = plane->id;  in skl_print_wm_changes()  local
2648 			old_wm = &old_pipe_wm->planes[plane_id];  in skl_print_wm_changes()
2649 			new_wm = &new_pipe_wm->planes[plane_id];  in skl_print_wm_changes()
2806 		enum plane_id plane_id = plane->id;  in skl_wm_add_affected_planes()  local
2832 		new_crtc_state->update_planes |= BIT(plane_id);  in skl_wm_add_affected_planes()
2936 	enum plane_id plane_id;  in skl_pipe_wm_get_hw_state()  local
2940 	for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_pipe_wm_get_hw_state()
2941 		struct skl_plane_wm *wm = &out->planes[plane_id];  in skl_pipe_wm_get_hw_state()
2944 			if (plane_id != PLANE_CURSOR)  in skl_pipe_wm_get_hw_state()
2945 				val = intel_de_read(i915, PLANE_WM(pipe, plane_id, level));  in skl_pipe_wm_get_hw_state()
2952 		if (plane_id != PLANE_CURSOR)  in skl_pipe_wm_get_hw_state()
2953 			val = intel_de_read(i915, PLANE_WM_TRANS(pipe, plane_id));  in skl_pipe_wm_get_hw_state()
2960 			if (plane_id != PLANE_CURSOR)  in skl_pipe_wm_get_hw_state()
2961 				val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id));  in skl_pipe_wm_get_hw_state()
2967 			if (plane_id != PLANE_CURSOR)  in skl_pipe_wm_get_hw_state()
2968 				val = intel_de_read(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id));  in skl_pipe_wm_get_hw_state()
2997 		enum plane_id plane_id;  in skl_wm_get_hw_state()  local
3008 		for_each_plane_id_on_crtc(crtc, plane_id) {  in skl_wm_get_hw_state()
3010 				&crtc_state->wm.skl.plane_ddb[plane_id];  in skl_wm_get_hw_state()
3012 				&crtc_state->wm.skl.plane_ddb_y[plane_id];  in skl_wm_get_hw_state()
3018 						   plane_id, ddb, ddb_y);  in skl_wm_get_hw_state()