367 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
389 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_can_enable_sagv()
412 			&crtc_state->wm.skl.optimal.planes[plane_id];  in tgl_crtc_can_enable_sagv()
457 		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;  in intel_compute_sagv_mask()
479 		 * other crtcs can't be allowed to use the more optimal  in intel_compute_sagv_mask()
1551 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1599 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1630 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
1658 			&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_crtc_allocate_plane_ddb()
2254 		const struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];  in skl_max_wm0_lines()
2315 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_wm_check_vblank()
2334 				&crtc_state->wm.skl.optimal.planes[plane_id];  in skl_wm_check_vblank()
2371 	crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;  in skl_build_pipe_wm()
2624 		old_pipe_wm = &old_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
2625 		new_pipe_wm = &new_crtc_state->wm.skl.optimal;  in skl_print_wm_changes()
2818 						 &old_crtc_state->wm.skl.optimal,  in skl_wm_add_affected_planes()
2819 						 &new_crtc_state->wm.skl.optimal))  in skl_wm_add_affected_planes()
3000 		memset(&crtc_state->wm.skl.optimal, 0,  in skl_wm_get_hw_state()
3001 		       sizeof(crtc_state->wm.skl.optimal));  in skl_wm_get_hw_state()
3003 			skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);  in skl_wm_get_hw_state()
3004 		crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;  in skl_wm_get_hw_state()
3136 	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;  in intel_wm_state_verify()