Lines Matching refs:display
201 static bool __intel_display_power_is_enabled(struct intel_display *display,
207 if (pm_runtime_suspended(display->drm->dev))
212 for_each_power_domain_well_reverse(display, power_well, domain) {
227 * @display: display device instance
242 bool intel_display_power_is_enabled(struct intel_display *display,
245 struct i915_power_domains *power_domains = &display->power.domains;
249 ret = __intel_display_power_is_enabled(display, domain);
256 sanitize_target_dc_state(struct intel_display *display,
259 struct i915_power_domains *power_domains = &display->power.domains;
283 * @display: display device
290 void intel_display_power_set_target_dc_state(struct intel_display *display,
295 struct i915_power_domains *power_domains = &display->power.domains;
298 power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
300 if (drm_WARN_ON(display->drm, !power_well))
303 state = sanitize_target_dc_state(display, state);
308 dc_off_enabled = intel_power_well_is_enabled(display, power_well);
314 intel_power_well_enable(display, power_well);
319 intel_power_well_disable(display, power_well);
339 struct intel_display *display = container_of(power_domains,
343 return !drm_WARN_ON(display->drm,
352 struct intel_display *display = container_of(power_domains,
361 err |= drm_WARN_ON(display->drm,
366 err |= drm_WARN_ON(display->drm,
375 struct intel_display *display = container_of(power_domains,
380 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
382 drm_dbg_kms(display->drm, "%s use_count %d\n",
390 struct intel_display *display = container_of(power_domains,
394 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n",
455 intel_display_power_grab_async_put_ref(struct intel_display *display,
458 struct drm_i915_private *dev_priv = to_i915(display->drm);
459 struct i915_power_domains *power_domains = &display->power.domains;
485 __intel_display_power_get_domain(struct intel_display *display,
488 struct i915_power_domains *power_domains = &display->power.domains;
491 if (intel_display_power_grab_async_put_ref(display, domain))
494 for_each_power_domain_well(display, power_well, domain)
495 intel_power_well_get(display, power_well);
502 * @display: display device instance
512 intel_wakeref_t intel_display_power_get(struct intel_display *display,
515 struct drm_i915_private *dev_priv = to_i915(display->drm);
516 struct i915_power_domains *power_domains = &display->power.domains;
520 __intel_display_power_get_domain(display, domain);
527 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
528 * @display: display device instance
539 intel_display_power_get_if_enabled(struct intel_display *display,
542 struct drm_i915_private *dev_priv = to_i915(display->drm);
543 struct i915_power_domains *power_domains = &display->power.domains;
553 if (__intel_display_power_is_enabled(display, domain)) {
554 __intel_display_power_get_domain(display, domain);
571 __intel_display_power_put_domain(struct intel_display *display,
574 struct i915_power_domains *power_domains = &display->power.domains;
579 drm_WARN(display->drm, !power_domains->domain_use_count[domain],
583 drm_WARN(display->drm,
590 for_each_power_domain_well_reverse(display, power_well, domain)
591 intel_power_well_put(display, power_well);
594 static void __intel_display_power_put(struct intel_display *display,
597 struct i915_power_domains *power_domains = &display->power.domains;
600 __intel_display_power_put_domain(display, domain);
609 struct intel_display *display = container_of(power_domains,
612 drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
614 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq,
623 struct intel_display *display = container_of(power_domains,
626 struct drm_i915_private *dev_priv = to_i915(display->drm);
636 __intel_display_power_put_domain(display, domain);
645 struct intel_display *display = container_of(work, struct intel_display,
647 struct drm_i915_private *dev_priv = to_i915(display->drm);
648 struct i915_power_domains *power_domains = &display->power.domains;
698 * @display: display device instance
709 void __intel_display_power_put_async(struct intel_display *display,
714 struct drm_i915_private *i915 = to_i915(display->drm);
715 struct i915_power_domains *power_domains = &display->power.domains;
724 __intel_display_power_put_domain(display, domain);
729 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1);
755 * intel_display_power_flush_work - flushes the async display power disabling work
756 * @display: display device instance
766 void intel_display_power_flush_work(struct intel_display *display)
768 struct drm_i915_private *i915 = to_i915(display->drm);
769 struct i915_power_domains *power_domains = &display->power.domains;
793 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
794 * @display: display device instance
800 intel_display_power_flush_work_sync(struct intel_display *display)
802 struct i915_power_domains *power_domains = &display->power.domains;
804 intel_display_power_flush_work(display);
809 drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
815 * @display: display device instance
823 void intel_display_power_put(struct intel_display *display,
827 struct drm_i915_private *dev_priv = to_i915(display->drm);
829 __intel_display_power_put(display, domain);
835 * @display: display device instance
846 void intel_display_power_put_unchecked(struct intel_display *display,
849 struct drm_i915_private *dev_priv = to_i915(display->drm);
851 __intel_display_power_put(display, domain);
857 intel_display_power_get_in_set(struct intel_display *display,
863 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
865 wf = intel_display_power_get(display, domain);
873 intel_display_power_get_in_set_if_enabled(struct intel_display *display,
879 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
881 wf = intel_display_power_get_if_enabled(display, domain);
894 intel_display_power_put_mask_in_set(struct intel_display *display,
900 drm_WARN_ON(display->drm,
909 intel_display_power_put(display, domain, wf);
923 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
929 if (!HAS_DISPLAY(display))
932 if (DISPLAY_VER(display) >= 20)
934 else if (display->platform.dg2)
936 else if (display->platform.dg1)
938 else if (DISPLAY_VER(display) >= 12)
940 else if (display->platform.geminilake || display->platform.broxton)
942 else if (DISPLAY_VER(display) >= 9)
952 mask = display->platform.geminilake || display->platform.broxton ||
953 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0;
955 if (!display->params.disable_power_well)
963 drm_dbg_kms(display->drm,
968 drm_err(display->drm,
988 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask);
995 * @display: display device instance
997 * Initializes the power domain structures for @display depending upon the
1000 int intel_power_domains_init(struct intel_display *display)
1002 struct i915_power_domains *power_domains = &display->power.domains;
1004 display->params.disable_power_well =
1005 sanitize_disable_power_well_option(display->params.disable_power_well);
1007 get_allowed_dc_mask(display, display->params.enable_dc);
1010 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
1022 * @display: display device instance
1026 void intel_power_domains_cleanup(struct intel_display *display)
1028 intel_display_power_map_cleanup(&display->power.domains);
1031 static void intel_power_domains_sync_hw(struct intel_display *display)
1033 struct i915_power_domains *power_domains = &display->power.domains;
1037 for_each_power_well(display, power_well)
1038 intel_power_well_sync_hw(display, power_well);
1042 static void gen9_dbuf_slice_set(struct intel_display *display,
1048 intel_de_rmw(display, reg, DBUF_POWER_REQUEST,
1050 intel_de_posting_read(display, reg);
1053 state = intel_de_read(display, reg) & DBUF_POWER_STATE;
1054 drm_WARN(display->drm, enable != state,
1059 void gen9_dbuf_slices_update(struct intel_display *display,
1062 struct i915_power_domains *power_domains = &display->power.domains;
1063 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;
1066 drm_WARN(display->drm, req_slices & ~slice_mask,
1070 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n",
1082 for_each_dbuf_slice(display, slice)
1083 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice));
1085 display->dbuf.enabled_slices = req_slices;
1090 static void gen9_dbuf_enable(struct intel_display *display)
1094 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display);
1096 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;
1098 if (DISPLAY_VER(display) >= 14)
1099 intel_pmdemand_program_dbuf(display, slices_mask);
1105 gen9_dbuf_slices_update(display, slices_mask);
1108 static void gen9_dbuf_disable(struct intel_display *display)
1110 gen9_dbuf_slices_update(display, 0);
1112 if (DISPLAY_VER(display) >= 14)
1113 intel_pmdemand_program_dbuf(display, 0);
1116 static void gen12_dbuf_slices_config(struct intel_display *display)
1120 for_each_dbuf_slice(display, slice)
1121 intel_de_rmw(display, DBUF_CTL_S(slice),
1126 static void icl_mbus_init(struct intel_display *display)
1128 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask;
1131 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1148 if (DISPLAY_VER(display) == 12)
1152 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);
1155 static void hsw_assert_cdclk(struct intel_display *display)
1157 u32 val = intel_de_read(display, LCPLL_CTL);
1166 drm_err(display->drm, "CDCLK source is not LCPLL\n");
1169 drm_err(display->drm, "LCPLL is disabled\n");
1172 drm_err(display->drm, "LCPLL not using non-SSC reference\n");
1175 static void assert_can_disable_lcpll(struct intel_display *display)
1177 struct drm_i915_private *dev_priv = to_i915(display->drm);
1180 for_each_intel_crtc(display->drm, crtc)
1181 INTEL_DISPLAY_STATE_WARN(display, crtc->active,
1185 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),
1187 INTEL_DISPLAY_STATE_WARN(display,
1188 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,
1190 INTEL_DISPLAY_STATE_WARN(display,
1191 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1193 INTEL_DISPLAY_STATE_WARN(display,
1194 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1196 INTEL_DISPLAY_STATE_WARN(display,
1197 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,
1199 INTEL_DISPLAY_STATE_WARN(display,
1200 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1202 if (display->platform.haswell)
1203 INTEL_DISPLAY_STATE_WARN(display,
1204 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1206 INTEL_DISPLAY_STATE_WARN(display,
1207 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1209 INTEL_DISPLAY_STATE_WARN(display,
1210 (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
1212 INTEL_DISPLAY_STATE_WARN(display,
1213 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1222 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv),
1226 static u32 hsw_read_dcomp(struct intel_display *display)
1228 if (display->platform.haswell)
1229 return intel_de_read(display, D_COMP_HSW);
1231 return intel_de_read(display, D_COMP_BDW);
1234 static void hsw_write_dcomp(struct intel_display *display, u32 val)
1236 struct drm_i915_private *dev_priv = to_i915(display->drm);
1238 if (display->platform.haswell) {
1240 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");
1242 intel_de_write(display, D_COMP_BDW, val);
1243 intel_de_posting_read(display, D_COMP_BDW);
1249 * - Sequence for display software to disable LCPLL
1250 * - Sequence for display software to allow package C8+
1252 * register. Callers should take care of disabling all the display engine
1255 static void hsw_disable_lcpll(struct intel_display *display,
1260 assert_can_disable_lcpll(display);
1262 val = intel_de_read(display, LCPLL_CTL);
1266 intel_de_write(display, LCPLL_CTL, val);
1268 if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
1270 drm_err(display->drm, "Switching to FCLK failed\n");
1272 val = intel_de_read(display, LCPLL_CTL);
1276 intel_de_write(display, LCPLL_CTL, val);
1277 intel_de_posting_read(display, LCPLL_CTL);
1279 if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
1280 drm_err(display->drm, "LCPLL still locked\n");
1282 val = hsw_read_dcomp(display);
1284 hsw_write_dcomp(display, val);
1287 if (wait_for((hsw_read_dcomp(display) &
1289 drm_err(display->drm, "D_COMP RCOMP still in progress\n");
1292 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);
1293 intel_de_posting_read(display, LCPLL_CTL);
1301 static void hsw_restore_lcpll(struct intel_display *display)
1303 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
1306 val = intel_de_read(display, LCPLL_CTL);
1320 intel_de_write(display, LCPLL_CTL, val);
1321 intel_de_posting_read(display, LCPLL_CTL);
1324 val = hsw_read_dcomp(display);
1327 hsw_write_dcomp(display, val);
1329 val = intel_de_read(display, LCPLL_CTL);
1331 intel_de_write(display, LCPLL_CTL, val);
1333 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
1334 drm_err(display->drm, "LCPLL not locked yet\n");
1337 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
1339 if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
1341 drm_err(display->drm,
1347 intel_update_cdclk(display);
1348 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1374 static void hsw_enable_pc8(struct intel_display *display)
1376 struct drm_i915_private *dev_priv = to_i915(display->drm);
1378 drm_dbg_kms(display->drm, "Enabling package C8+\n");
1381 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1385 hsw_disable_lcpll(display, true, true);
1388 static void hsw_disable_pc8(struct intel_display *display)
1390 struct drm_i915_private *dev_priv = to_i915(display->drm);
1392 drm_dbg_kms(display->drm, "Disabling package C8+\n");
1394 hsw_restore_lcpll(display);
1397 /* Many display registers don't survive PC8+ */
1403 static void intel_pch_reset_handshake(struct intel_display *display,
1409 if (display->platform.ivybridge) {
1417 if (DISPLAY_VER(display) >= 14)
1420 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);
1423 static void skl_display_core_init(struct intel_display *display,
1426 struct drm_i915_private *dev_priv = to_i915(display->drm);
1427 struct i915_power_domains *power_domains = &display->power.domains;
1430 gen9_set_dc_state(display, DC_STATE_DISABLE);
1433 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv));
1435 if (!HAS_DISPLAY(display))
1441 well = lookup_power_well(display, SKL_DISP_PW_1);
1442 intel_power_well_enable(display, well);
1444 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO);
1445 intel_power_well_enable(display, well);
1449 intel_cdclk_init_hw(display);
1451 gen9_dbuf_enable(display);
1454 intel_dmc_load_program(display);
1457 static void skl_display_core_uninit(struct intel_display *display)
1459 struct i915_power_domains *power_domains = &display->power.domains;
1462 if (!HAS_DISPLAY(display))
1465 gen9_disable_dc_states(display);
1468 gen9_dbuf_disable(display);
1470 intel_cdclk_uninit_hw(display);
1483 well = lookup_power_well(display, SKL_DISP_PW_1);
1484 intel_power_well_disable(display, well);
1491 static void bxt_display_core_init(struct intel_display *display, bool resume)
1493 struct i915_power_domains *power_domains = &display->power.domains;
1496 gen9_set_dc_state(display, DC_STATE_DISABLE);
1504 intel_pch_reset_handshake(display, false);
1506 if (!HAS_DISPLAY(display))
1512 well = lookup_power_well(display, SKL_DISP_PW_1);
1513 intel_power_well_enable(display, well);
1517 intel_cdclk_init_hw(display);
1519 gen9_dbuf_enable(display);
1522 intel_dmc_load_program(display);
1525 static void bxt_display_core_uninit(struct intel_display *display)
1527 struct i915_power_domains *power_domains = &display->power.domains;
1530 if (!HAS_DISPLAY(display))
1533 gen9_disable_dc_states(display);
1536 gen9_dbuf_disable(display);
1538 intel_cdclk_uninit_hw(display);
1549 well = lookup_power_well(display, SKL_DISP_PW_1);
1550 intel_power_well_disable(display, well);
1587 static void tgl_bw_buddy_init(struct intel_display *display)
1589 struct drm_i915_private *dev_priv = to_i915(display->drm);
1593 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;
1597 if (display->platform.dgfx && !display->platform.dg1)
1600 if (display->platform.alderlake_s ||
1601 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)))
1613 drm_dbg_kms(display->drm,
1616 intel_de_write(display, BW_BUDDY_CTL(i),
1620 intel_de_write(display, BW_BUDDY_PAGE_MASK(i),
1624 if (DISPLAY_VER(display) == 12)
1625 intel_de_rmw(display, BW_BUDDY_CTL(i),
1632 static void icl_display_core_init(struct intel_display *display,
1635 struct drm_i915_private *dev_priv = to_i915(display->drm);
1636 struct i915_power_domains *power_domains = &display->power.domains;
1639 gen9_set_dc_state(display, DC_STATE_DISABLE);
1644 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
1648 intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv));
1650 if (!HAS_DISPLAY(display))
1654 intel_combo_phy_init(display);
1661 well = lookup_power_well(display, SKL_DISP_PW_1);
1662 intel_power_well_enable(display, well);
1665 if (DISPLAY_VER(display) == 14)
1666 intel_de_rmw(display, DC_STATE_EN,
1670 intel_cdclk_init_hw(display);
1672 if (DISPLAY_VER(display) == 12 || display->platform.dg2)
1673 gen12_dbuf_slices_config(display);
1676 gen9_dbuf_enable(display);
1679 icl_mbus_init(display);
1682 if (DISPLAY_VER(display) >= 12)
1683 tgl_bw_buddy_init(display);
1686 if (display->platform.dg2)
1687 intel_snps_phy_wait_for_calibration(display);
1690 if (DISPLAY_VERx100(display) == 1401)
1691 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
1694 intel_dmc_load_program(display);
1697 if (IS_DISPLAY_VERx100(display, 1200, 1300))
1698 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0,
1703 if (DISPLAY_VER(display) == 13)
1704 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
1707 if (DISPLAY_VER(display) == 20) {
1708 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1710 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1715 static void icl_display_core_uninit(struct intel_display *display)
1717 struct i915_power_domains *power_domains = &display->power.domains;
1720 if (!HAS_DISPLAY(display))
1723 gen9_disable_dc_states(display);
1724 intel_dmc_disable_program(display);
1726 /* 1. Disable all display engine functions -> already done */
1729 gen9_dbuf_disable(display);
1732 intel_cdclk_uninit_hw(display);
1734 if (DISPLAY_VER(display) == 14)
1735 intel_de_rmw(display, DC_STATE_EN, 0,
1744 well = lookup_power_well(display, SKL_DISP_PW_1);
1745 intel_power_well_disable(display, well);
1749 intel_combo_phy_uninit(display);
1752 static void chv_phy_control_init(struct intel_display *display)
1755 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
1757 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);
1766 display->power.chv_phy_control =
1780 if (intel_power_well_is_enabled(display, cmn_bc)) {
1781 u32 status = intel_de_read(display, DPLL(display, PIPE_A));
1788 display->power.chv_phy_control |=
1791 display->power.chv_phy_control |=
1798 display->power.chv_phy_control |=
1801 display->power.chv_phy_control |=
1804 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1806 display->power.chv_phy_assert[DPIO_PHY0] = false;
1808 display->power.chv_phy_assert[DPIO_PHY0] = true;
1811 if (intel_power_well_is_enabled(display, cmn_d)) {
1812 u32 status = intel_de_read(display, DPIO_PHY_STATUS);
1820 display->power.chv_phy_control |=
1823 display->power.chv_phy_control |=
1826 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1828 display->power.chv_phy_assert[DPIO_PHY1] = false;
1830 display->power.chv_phy_assert[DPIO_PHY1] = true;
1833 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n",
1834 display->power.chv_phy_control);
1839 static void vlv_cmnlane_wa(struct intel_display *display)
1842 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
1844 lookup_power_well(display, VLV_DISP_PW_DISP2D);
1846 /* If the display might be already active skip this */
1847 if (intel_power_well_is_enabled(display, cmn) &&
1848 intel_power_well_is_enabled(display, disp2d) &&
1849 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)
1852 drm_dbg_kms(display->drm, "toggling display PHY side reset\n");
1855 intel_power_well_enable(display, disp2d);
1864 intel_power_well_disable(display, cmn);
1867 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)
1869 struct drm_i915_private *dev_priv = to_i915(display->drm);
1879 static void assert_ved_power_gated(struct intel_display *display)
1881 drm_WARN(display->drm,
1882 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0),
1886 static void assert_isp_power_gated(struct intel_display *display)
1894 drm_WARN(display->drm, !pci_dev_present(isp_ids) &&
1895 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0),
1899 static void intel_power_domains_verify_state(struct intel_display *display);
1903 * @display: display device instance
1917 void intel_power_domains_init_hw(struct intel_display *display, bool resume)
1919 struct drm_i915_private *i915 = to_i915(display->drm);
1920 struct i915_power_domains *power_domains = &display->power.domains;
1924 if (DISPLAY_VER(display) >= 11) {
1925 icl_display_core_init(display, resume);
1926 } else if (display->platform.geminilake || display->platform.broxton) {
1927 bxt_display_core_init(display, resume);
1928 } else if (DISPLAY_VER(display) == 9) {
1929 skl_display_core_init(display, resume);
1930 } else if (display->platform.cherryview) {
1932 chv_phy_control_init(display);
1934 assert_isp_power_gated(display);
1935 } else if (display->platform.valleyview) {
1937 vlv_cmnlane_wa(display);
1939 assert_ved_power_gated(display);
1940 assert_isp_power_gated(display);
1941 } else if (display->platform.broadwell || display->platform.haswell) {
1942 hsw_assert_cdclk(display);
1943 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915));
1944 } else if (display->platform.ivybridge) {
1945 intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915));
1950 * initialization and to make sure we keep BIOS enabled display HW
1951 * resources powered until display HW readout is complete. We drop
1954 drm_WARN_ON(display->drm, power_domains->init_wakeref);
1956 intel_display_power_get(display, POWER_DOMAIN_INIT);
1959 if (!display->params.disable_power_well) {
1960 drm_WARN_ON(display->drm, power_domains->disable_wakeref);
1961 display->power.domains.disable_wakeref = intel_display_power_get(display,
1964 intel_power_domains_sync_hw(display);
1971 * @display: display device instance
1973 * De-initializes the display power domain HW state. It also ensures that the
1980 void intel_power_domains_driver_remove(struct intel_display *display)
1982 struct drm_i915_private *i915 = to_i915(display->drm);
1984 fetch_and_zero(&display->power.domains.init_wakeref);
1987 if (!display->params.disable_power_well)
1988 intel_display_power_put(display, POWER_DOMAIN_INIT,
1989 fetch_and_zero(&display->power.domains.disable_wakeref));
1991 intel_display_power_flush_work_sync(display);
1993 intel_power_domains_verify_state(display);
2001 * @display: display device instance
2004 * The function will disable all display power wells that BIOS has enabled
2009 void intel_power_domains_sanitize_state(struct intel_display *display)
2011 struct i915_power_domains *power_domains = &display->power.domains;
2016 for_each_power_well_reverse(display, power_well) {
2018 !intel_power_well_is_enabled(display, power_well))
2021 drm_dbg_kms(display->drm,
2024 intel_power_well_disable(display, power_well);
2031 * intel_power_domains_enable - enable toggling of display power wells
2032 * @display: display device instance
2034 * Enable the ondemand enabling/disabling of the display power wells. Note that
2036 * only at specific points of the display modeset sequence, thus they are not
2039 * of display HW readout (which will acquire the power references reflecting
2042 void intel_power_domains_enable(struct intel_display *display)
2045 fetch_and_zero(&display->power.domains.init_wakeref);
2047 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
2048 intel_power_domains_verify_state(display);
2052 * intel_power_domains_disable - disable toggling of display power wells
2053 * @display: display device instance
2055 * Disable the ondemand enabling/disabling of the display power wells. See
2058 void intel_power_domains_disable(struct intel_display *display)
2060 struct i915_power_domains *power_domains = &display->power.domains;
2062 drm_WARN_ON(display->drm, power_domains->init_wakeref);
2064 intel_display_power_get(display, POWER_DOMAIN_INIT);
2066 intel_power_domains_verify_state(display);
2071 * @display: display device instance
2080 void intel_power_domains_suspend(struct intel_display *display, bool s2idle)
2082 struct i915_power_domains *power_domains = &display->power.domains;
2086 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
2096 intel_dmc_has_payload(display)) {
2097 intel_display_power_flush_work(display);
2098 intel_power_domains_verify_state(display);
2106 if (!display->params.disable_power_well)
2107 intel_display_power_put(display, POWER_DOMAIN_INIT,
2108 fetch_and_zero(&display->power.domains.disable_wakeref));
2110 intel_display_power_flush_work(display);
2111 intel_power_domains_verify_state(display);
2113 if (DISPLAY_VER(display) >= 11)
2114 icl_display_core_uninit(display);
2115 else if (display->platform.geminilake || display->platform.broxton)
2116 bxt_display_core_uninit(display);
2117 else if (DISPLAY_VER(display) == 9)
2118 skl_display_core_uninit(display);
2125 * @display: display device instance
2133 void intel_power_domains_resume(struct intel_display *display)
2135 struct i915_power_domains *power_domains = &display->power.domains;
2138 intel_power_domains_init_hw(display, true);
2141 drm_WARN_ON(display->drm, power_domains->init_wakeref);
2143 intel_display_power_get(display, POWER_DOMAIN_INIT);
2146 intel_power_domains_verify_state(display);
2151 static void intel_power_domains_dump_info(struct intel_display *display)
2153 struct i915_power_domains *power_domains = &display->power.domains;
2156 for_each_power_well(display, power_well) {
2159 drm_dbg_kms(display->drm, "%-25s %d\n",
2163 drm_dbg_kms(display->drm, " %-23s %d\n",
2171 * @display: display device instance
2179 static void intel_power_domains_verify_state(struct intel_display *display)
2181 struct i915_power_domains *power_domains = &display->power.domains;
2190 for_each_power_well(display, power_well) {
2195 enabled = intel_power_well_is_enabled(display, power_well);
2199 drm_err(display->drm,
2209 drm_err(display->drm,
2223 intel_power_domains_dump_info(display);
2233 static void intel_power_domains_verify_state(struct intel_display *display)
2239 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle)
2241 struct drm_i915_private *i915 = to_i915(display->drm);
2243 intel_power_domains_suspend(display, s2idle);
2245 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
2246 display->platform.broxton) {
2247 bxt_enable_dc9(display);
2248 } else if (display->platform.haswell || display->platform.broadwell) {
2249 hsw_enable_pc8(display);
2257 void intel_display_power_resume_early(struct intel_display *display)
2259 struct drm_i915_private *i915 = to_i915(display->drm);
2261 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
2262 display->platform.broxton) {
2263 gen9_sanitize_dc_state(display);
2264 bxt_disable_dc9(display);
2265 } else if (display->platform.haswell || display->platform.broadwell) {
2266 hsw_disable_pc8(display);
2273 intel_power_domains_resume(display);
2276 void intel_display_power_suspend(struct intel_display *display)
2278 if (DISPLAY_VER(display) >= 11) {
2279 icl_display_core_uninit(display);
2280 bxt_enable_dc9(display);
2281 } else if (display->platform.geminilake || display->platform.broxton) {
2282 bxt_display_core_uninit(display);
2283 bxt_enable_dc9(display);
2284 } else if (display->platform.haswell || display->platform.broadwell) {
2285 hsw_enable_pc8(display);
2289 void intel_display_power_resume(struct intel_display *display)
2291 struct i915_power_domains *power_domains = &display->power.domains;
2293 if (DISPLAY_VER(display) >= 11) {
2294 bxt_disable_dc9(display);
2295 icl_display_core_init(display, true);
2296 if (intel_dmc_has_payload(display)) {
2298 skl_enable_dc6(display);
2300 gen9_enable_dc5(display);
2302 } else if (display->platform.geminilake || display->platform.broxton) {
2303 bxt_disable_dc9(display);
2304 bxt_display_core_init(display, true);
2305 if (intel_dmc_has_payload(display) &&
2307 gen9_enable_dc5(display);
2308 } else if (display->platform.haswell || display->platform.broadwell) {
2309 hsw_disable_pc8(display);
2313 void intel_display_power_debug(struct intel_display *display, struct seq_file *m)
2315 struct i915_power_domains *power_domains = &display->power.domains;
2463 intel_port_domains_for_platform(struct intel_display *display,
2467 if (DISPLAY_VER(display) >= 13) {
2470 } else if (DISPLAY_VER(display) >= 12) {
2473 } else if (DISPLAY_VER(display) >= 11) {
2483 intel_port_domains_for_port(struct intel_display *display, enum port port)
2489 intel_port_domains_for_platform(display, &domains, &domains_size);
2498 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port)
2500 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
2502 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
2509 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port)
2511 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
2513 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
2520 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch)
2526 intel_port_domains_for_platform(display, &domains, &domains_size);
2535 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch)
2537 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
2539 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
2546 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch)
2548 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
2550 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
2557 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch)
2559 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
2561 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))