Lines Matching full:display
207 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled() argument
213 if (intel_display_rpm_suspended(display)) in __intel_display_power_is_enabled()
218 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
233 * @display: display device instance
248 bool intel_display_power_is_enabled(struct intel_display *display, in intel_display_power_is_enabled() argument
251 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
255 ret = __intel_display_power_is_enabled(display, domain); in intel_display_power_is_enabled()
262 sanitize_target_dc_state(struct intel_display *display, in sanitize_target_dc_state() argument
265 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
289 * @display: display device
296 void intel_display_power_set_target_dc_state(struct intel_display *display, in intel_display_power_set_target_dc_state() argument
301 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_set_target_dc_state()
304 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); in intel_display_power_set_target_dc_state()
306 if (drm_WARN_ON(display->drm, !power_well)) in intel_display_power_set_target_dc_state()
309 state = sanitize_target_dc_state(display, state); in intel_display_power_set_target_dc_state()
314 dc_off_enabled = intel_power_well_is_enabled(display, power_well); in intel_display_power_set_target_dc_state()
320 intel_power_well_enable(display, power_well); in intel_display_power_set_target_dc_state()
325 intel_power_well_disable(display, power_well); in intel_display_power_set_target_dc_state()
333 * @display: display device
339 u32 intel_display_power_get_current_dc_state(struct intel_display *display) in intel_display_power_get_current_dc_state() argument
342 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get_current_dc_state()
346 power_well = lookup_power_well(display, SKL_DISP_DC_OFF); in intel_display_power_get_current_dc_state()
348 if (drm_WARN_ON(display->drm, !power_well)) in intel_display_power_get_current_dc_state()
351 current_dc_state = intel_power_well_is_enabled(display, power_well) ? in intel_display_power_get_current_dc_state()
374 struct intel_display *display = container_of(power_domains, in assert_async_put_domain_masks_disjoint() local
378 return !drm_WARN_ON(display->drm, in assert_async_put_domain_masks_disjoint()
387 struct intel_display *display = container_of(power_domains, in __async_put_domains_state_ok() local
396 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
401 err |= drm_WARN_ON(display->drm, in __async_put_domains_state_ok()
410 struct intel_display *display = container_of(power_domains, in print_power_domains() local
415 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); in print_power_domains()
417 drm_dbg_kms(display->drm, "%s use_count %d\n", in print_power_domains()
425 struct intel_display *display = container_of(power_domains, in print_async_put_domains_state() local
429 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", in print_async_put_domains_state()
490 intel_display_power_grab_async_put_ref(struct intel_display *display, in intel_display_power_grab_async_put_ref() argument
493 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_grab_async_put_ref()
510 intel_display_rpm_put_raw(display, in intel_display_power_grab_async_put_ref()
519 __intel_display_power_get_domain(struct intel_display *display, in __intel_display_power_get_domain() argument
522 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_get_domain()
525 if (intel_display_power_grab_async_put_ref(display, domain)) in __intel_display_power_get_domain()
528 for_each_power_domain_well(display, power_well, domain) in __intel_display_power_get_domain()
529 intel_power_well_get(display, power_well); in __intel_display_power_get_domain()
536 * @display: display device instance
546 intel_wakeref_t intel_display_power_get(struct intel_display *display, in intel_display_power_get() argument
549 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get()
552 wakeref = intel_display_rpm_get(display); in intel_display_power_get()
555 __intel_display_power_get_domain(display, domain); in intel_display_power_get()
562 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
563 * @display: display device instance
574 intel_display_power_get_if_enabled(struct intel_display *display, in intel_display_power_get_if_enabled() argument
577 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_get_if_enabled()
581 wakeref = intel_display_rpm_get_if_in_use(display); in intel_display_power_get_if_enabled()
587 if (__intel_display_power_is_enabled(display, domain)) { in intel_display_power_get_if_enabled()
588 __intel_display_power_get_domain(display, domain); in intel_display_power_get_if_enabled()
597 intel_display_rpm_put(display, wakeref); in intel_display_power_get_if_enabled()
605 __intel_display_power_put_domain(struct intel_display *display, in __intel_display_power_put_domain() argument
608 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_domain()
613 drm_WARN(display->drm, !power_domains->domain_use_count[domain], in __intel_display_power_put_domain()
617 drm_WARN(display->drm, in __intel_display_power_put_domain()
624 for_each_power_domain_well_reverse(display, power_well, domain) in __intel_display_power_put_domain()
625 intel_power_well_put(display, power_well); in __intel_display_power_put_domain()
628 static void __intel_display_power_put(struct intel_display *display, in __intel_display_power_put() argument
631 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put()
634 __intel_display_power_put_domain(display, domain); in __intel_display_power_put()
643 struct intel_display *display = container_of(power_domains, in queue_async_put_domains_work() local
646 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in queue_async_put_domains_work()
648 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq, in queue_async_put_domains_work()
657 struct intel_display *display = container_of(power_domains, in release_async_put_domains() local
663 wakeref = intel_display_rpm_get_noresume(display); in release_async_put_domains()
668 __intel_display_power_put_domain(display, domain); in release_async_put_domains()
671 intel_display_rpm_put(display, wakeref); in release_async_put_domains()
677 struct intel_display *display = container_of(work, struct intel_display, in intel_display_power_put_async_work() local
679 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_put_async_work()
682 new_work_wakeref = intel_display_rpm_get_raw(display); in intel_display_power_put_async_work()
722 intel_display_rpm_put_raw(display, old_work_wakeref); in intel_display_power_put_async_work()
724 intel_display_rpm_put_raw(display, new_work_wakeref); in intel_display_power_put_async_work()
729 * @display: display device instance
740 void __intel_display_power_put_async(struct intel_display *display, in __intel_display_power_put_async() argument
745 struct i915_power_domains *power_domains = &display->power.domains; in __intel_display_power_put_async()
748 work_wakeref = intel_display_rpm_get_raw(display); in __intel_display_power_put_async()
755 __intel_display_power_put_domain(display, domain); in __intel_display_power_put_async()
760 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); in __intel_display_power_put_async()
780 intel_display_rpm_put_raw(display, work_wakeref); in __intel_display_power_put_async()
782 intel_display_rpm_put(display, wakeref); in __intel_display_power_put_async()
786 * intel_display_power_flush_work - flushes the async display power disabling work
787 * @display: display device instance
797 void intel_display_power_flush_work(struct intel_display *display) in intel_display_power_flush_work() argument
799 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work()
819 intel_display_rpm_put_raw(display, work_wakeref); in intel_display_power_flush_work()
823 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
824 * @display: display device instance
830 intel_display_power_flush_work_sync(struct intel_display *display) in intel_display_power_flush_work_sync() argument
832 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_flush_work_sync()
834 intel_display_power_flush_work(display); in intel_display_power_flush_work_sync()
839 drm_WARN_ON(display->drm, power_domains->async_put_wakeref); in intel_display_power_flush_work_sync()
845 * @display: display device instance
853 void intel_display_power_put(struct intel_display *display, in intel_display_power_put() argument
857 __intel_display_power_put(display, domain); in intel_display_power_put()
858 intel_display_rpm_put(display, wakeref); in intel_display_power_put()
863 * @display: display device instance
874 void intel_display_power_put_unchecked(struct intel_display *display, in intel_display_power_put_unchecked() argument
877 __intel_display_power_put(display, domain); in intel_display_power_put_unchecked()
878 intel_display_rpm_put_unchecked(display); in intel_display_power_put_unchecked()
883 intel_display_power_get_in_set(struct intel_display *display, in intel_display_power_get_in_set() argument
889 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set()
891 wf = intel_display_power_get(display, domain); in intel_display_power_get_in_set()
899 intel_display_power_get_in_set_if_enabled(struct intel_display *display, in intel_display_power_get_in_set_if_enabled() argument
905 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); in intel_display_power_get_in_set_if_enabled()
907 wf = intel_display_power_get_if_enabled(display, domain); in intel_display_power_get_in_set_if_enabled()
920 intel_display_power_put_mask_in_set(struct intel_display *display, in intel_display_power_put_mask_in_set() argument
926 drm_WARN_ON(display->drm, in intel_display_power_put_mask_in_set()
935 intel_display_power_put(display, domain, wf); in intel_display_power_put_mask_in_set()
949 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) in get_allowed_dc_mask() argument
955 if (!HAS_DISPLAY(display)) in get_allowed_dc_mask()
958 if (DISPLAY_VER(display) >= 20) in get_allowed_dc_mask()
960 else if (display->platform.dg2) in get_allowed_dc_mask()
962 else if (display->platform.dg1) in get_allowed_dc_mask()
964 else if (DISPLAY_VER(display) >= 12) in get_allowed_dc_mask()
966 else if (display->platform.geminilake || display->platform.broxton) in get_allowed_dc_mask()
968 else if (DISPLAY_VER(display) >= 9) in get_allowed_dc_mask()
978 mask = display->platform.geminilake || display->platform.broxton || in get_allowed_dc_mask()
979 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; in get_allowed_dc_mask()
981 if (!display->params.disable_power_well) in get_allowed_dc_mask()
989 drm_dbg_kms(display->drm, in get_allowed_dc_mask()
994 drm_err(display->drm, in get_allowed_dc_mask()
1014 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); in get_allowed_dc_mask()
1021 * @display: display device instance
1023 * Initializes the power domain structures for @display depending upon the
1026 int intel_power_domains_init(struct intel_display *display) in intel_power_domains_init() argument
1028 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init()
1030 display->params.disable_power_well = in intel_power_domains_init()
1031 sanitize_disable_power_well_option(display->params.disable_power_well); in intel_power_domains_init()
1033 get_allowed_dc_mask(display, display->params.enable_dc); in intel_power_domains_init()
1036 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); in intel_power_domains_init()
1048 * @display: display device instance
1052 void intel_power_domains_cleanup(struct intel_display *display) in intel_power_domains_cleanup() argument
1054 intel_display_power_map_cleanup(&display->power.domains); in intel_power_domains_cleanup()
1057 static void intel_power_domains_sync_hw(struct intel_display *display) in intel_power_domains_sync_hw() argument
1059 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sync_hw()
1063 for_each_power_well(display, power_well) in intel_power_domains_sync_hw()
1064 intel_power_well_sync_hw(display, power_well); in intel_power_domains_sync_hw()
1068 static void gen9_dbuf_slice_set(struct intel_display *display, in gen9_dbuf_slice_set() argument
1074 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, in gen9_dbuf_slice_set()
1076 intel_de_posting_read(display, reg); in gen9_dbuf_slice_set()
1079 state = intel_de_read(display, reg) & DBUF_POWER_STATE; in gen9_dbuf_slice_set()
1080 drm_WARN(display->drm, enable != state, in gen9_dbuf_slice_set()
1085 void gen9_dbuf_slices_update(struct intel_display *display, in gen9_dbuf_slices_update() argument
1088 struct i915_power_domains *power_domains = &display->power.domains; in gen9_dbuf_slices_update()
1089 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; in gen9_dbuf_slices_update()
1092 drm_WARN(display->drm, req_slices & ~slice_mask, in gen9_dbuf_slices_update()
1096 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", in gen9_dbuf_slices_update()
1108 for_each_dbuf_slice(display, slice) in gen9_dbuf_slices_update()
1109 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); in gen9_dbuf_slices_update()
1111 display->dbuf.enabled_slices = req_slices; in gen9_dbuf_slices_update()
1116 static void gen9_dbuf_enable(struct intel_display *display) in gen9_dbuf_enable() argument
1120 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display); in gen9_dbuf_enable()
1122 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; in gen9_dbuf_enable()
1124 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_enable()
1125 intel_pmdemand_program_dbuf(display, slices_mask); in gen9_dbuf_enable()
1131 gen9_dbuf_slices_update(display, slices_mask); in gen9_dbuf_enable()
1134 static void gen9_dbuf_disable(struct intel_display *display) in gen9_dbuf_disable() argument
1136 gen9_dbuf_slices_update(display, 0); in gen9_dbuf_disable()
1138 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_disable()
1139 intel_pmdemand_program_dbuf(display, 0); in gen9_dbuf_disable()
1142 static void gen12_dbuf_slices_config(struct intel_display *display) in gen12_dbuf_slices_config() argument
1146 for_each_dbuf_slice(display, slice) in gen12_dbuf_slices_config()
1147 intel_de_rmw(display, DBUF_CTL_S(slice), in gen12_dbuf_slices_config()
1152 static void icl_mbus_init(struct intel_display *display) in icl_mbus_init() argument
1154 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; in icl_mbus_init()
1157 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) in icl_mbus_init()
1174 if (DISPLAY_VER(display) == 12) in icl_mbus_init()
1178 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); in icl_mbus_init()
1181 static void hsw_assert_cdclk(struct intel_display *display) in hsw_assert_cdclk() argument
1183 u32 val = intel_de_read(display, LCPLL_CTL); in hsw_assert_cdclk()
1192 drm_err(display->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1195 drm_err(display->drm, "LCPLL is disabled\n"); in hsw_assert_cdclk()
1198 drm_err(display->drm, "LCPLL not using non-SSC reference\n"); in hsw_assert_cdclk()
1201 static void assert_can_disable_lcpll(struct intel_display *display) in assert_can_disable_lcpll() argument
1203 struct drm_i915_private *dev_priv = to_i915(display->drm); in assert_can_disable_lcpll()
1206 for_each_intel_crtc(display->drm, crtc) in assert_can_disable_lcpll()
1207 INTEL_DISPLAY_STATE_WARN(display, crtc->active, in assert_can_disable_lcpll()
1211 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2), in assert_can_disable_lcpll()
1212 "Display power well on\n"); in assert_can_disable_lcpll()
1213 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1214 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1216 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1217 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1219 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1220 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1222 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1223 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, in assert_can_disable_lcpll()
1225 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1226 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1228 if (display->platform.haswell) in assert_can_disable_lcpll()
1229 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1230 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1232 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1233 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
1235 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1236 …(intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABL… in assert_can_disable_lcpll()
1238 INTEL_DISPLAY_STATE_WARN(display, in assert_can_disable_lcpll()
1239 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE, in assert_can_disable_lcpll()
1248 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), in assert_can_disable_lcpll()
1252 static u32 hsw_read_dcomp(struct intel_display *display) in hsw_read_dcomp() argument
1254 if (display->platform.haswell) in hsw_read_dcomp()
1255 return intel_de_read(display, D_COMP_HSW); in hsw_read_dcomp()
1257 return intel_de_read(display, D_COMP_BDW); in hsw_read_dcomp()
1260 static void hsw_write_dcomp(struct intel_display *display, u32 val) in hsw_write_dcomp() argument
1262 if (display->platform.haswell) { in hsw_write_dcomp()
1263 if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val)) in hsw_write_dcomp()
1264 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); in hsw_write_dcomp()
1266 intel_de_write(display, D_COMP_BDW, val); in hsw_write_dcomp()
1267 intel_de_posting_read(display, D_COMP_BDW); in hsw_write_dcomp()
1273 * - Sequence for display software to disable LCPLL
1274 * - Sequence for display software to allow package C8+
1276 * register. Callers should take care of disabling all the display engine
1279 static void hsw_disable_lcpll(struct intel_display *display, in hsw_disable_lcpll() argument
1285 assert_can_disable_lcpll(display); in hsw_disable_lcpll()
1287 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1291 intel_de_write(display, LCPLL_CTL, val); in hsw_disable_lcpll()
1293 ret = intel_de_wait_custom(display, LCPLL_CTL, in hsw_disable_lcpll()
1297 drm_err(display->drm, "Switching to FCLK failed\n"); in hsw_disable_lcpll()
1299 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1303 intel_de_write(display, LCPLL_CTL, val); in hsw_disable_lcpll()
1304 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1306 if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) in hsw_disable_lcpll()
1307 drm_err(display->drm, "LCPLL still locked\n"); in hsw_disable_lcpll()
1309 val = hsw_read_dcomp(display); in hsw_disable_lcpll()
1311 hsw_write_dcomp(display, val); in hsw_disable_lcpll()
1314 ret = poll_timeout_us(val = hsw_read_dcomp(display), in hsw_disable_lcpll()
1318 drm_err(display->drm, "D_COMP RCOMP still in progress\n"); in hsw_disable_lcpll()
1321 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); in hsw_disable_lcpll()
1322 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1330 static void hsw_restore_lcpll(struct intel_display *display) in hsw_restore_lcpll() argument
1332 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); in hsw_restore_lcpll()
1336 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1350 intel_de_write(display, LCPLL_CTL, val); in hsw_restore_lcpll()
1351 intel_de_posting_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1354 val = hsw_read_dcomp(display); in hsw_restore_lcpll()
1357 hsw_write_dcomp(display, val); in hsw_restore_lcpll()
1359 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1361 intel_de_write(display, LCPLL_CTL, val); in hsw_restore_lcpll()
1363 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) in hsw_restore_lcpll()
1364 drm_err(display->drm, "LCPLL not locked yet\n"); in hsw_restore_lcpll()
1367 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); in hsw_restore_lcpll()
1369 ret = intel_de_wait_custom(display, LCPLL_CTL, in hsw_restore_lcpll()
1373 drm_err(display->drm, in hsw_restore_lcpll()
1379 intel_update_cdclk(display); in hsw_restore_lcpll()
1380 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in hsw_restore_lcpll()
1403 * For more, read "Display Sequences for Package C8" on the hardware
1406 static void hsw_enable_pc8(struct intel_display *display) in hsw_enable_pc8() argument
1408 drm_dbg_kms(display->drm, "Enabling package C8+\n"); in hsw_enable_pc8()
1410 if (HAS_PCH_LPT_LP(display)) in hsw_enable_pc8()
1411 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in hsw_enable_pc8()
1414 lpt_disable_clkout_dp(display); in hsw_enable_pc8()
1415 hsw_disable_lcpll(display, true, true); in hsw_enable_pc8()
1418 static void hsw_disable_pc8(struct intel_display *display) in hsw_disable_pc8() argument
1420 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); in hsw_disable_pc8()
1422 drm_dbg_kms(display->drm, "Disabling package C8+\n"); in hsw_disable_pc8()
1424 hsw_restore_lcpll(display); in hsw_disable_pc8()
1425 intel_init_pch_refclk(display); in hsw_disable_pc8()
1427 /* Many display registers don't survive PC8+ */ in hsw_disable_pc8()
1433 static void intel_pch_reset_handshake(struct intel_display *display, in intel_pch_reset_handshake() argument
1439 if (display->platform.ivybridge) { in intel_pch_reset_handshake()
1447 if (DISPLAY_VER(display) >= 14) in intel_pch_reset_handshake()
1450 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); in intel_pch_reset_handshake()
1453 static void skl_display_core_init(struct intel_display *display, in skl_display_core_init() argument
1456 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_init()
1459 gen9_set_dc_state(display, DC_STATE_DISABLE); in skl_display_core_init()
1462 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); in skl_display_core_init()
1464 if (!HAS_DISPLAY(display)) in skl_display_core_init()
1470 well = lookup_power_well(display, SKL_DISP_PW_1); in skl_display_core_init()
1471 intel_power_well_enable(display, well); in skl_display_core_init()
1473 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); in skl_display_core_init()
1474 intel_power_well_enable(display, well); in skl_display_core_init()
1478 intel_cdclk_init_hw(display); in skl_display_core_init()
1480 gen9_dbuf_enable(display); in skl_display_core_init()
1483 intel_dmc_load_program(display); in skl_display_core_init()
1486 static void skl_display_core_uninit(struct intel_display *display) in skl_display_core_uninit() argument
1488 struct i915_power_domains *power_domains = &display->power.domains; in skl_display_core_uninit()
1491 if (!HAS_DISPLAY(display)) in skl_display_core_uninit()
1494 gen9_disable_dc_states(display); in skl_display_core_uninit()
1497 gen9_dbuf_disable(display); in skl_display_core_uninit()
1499 intel_cdclk_uninit_hw(display); in skl_display_core_uninit()
1512 well = lookup_power_well(display, SKL_DISP_PW_1); in skl_display_core_uninit()
1513 intel_power_well_disable(display, well); in skl_display_core_uninit()
1520 static void bxt_display_core_init(struct intel_display *display, bool resume) in bxt_display_core_init() argument
1522 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_init()
1525 gen9_set_dc_state(display, DC_STATE_DISABLE); in bxt_display_core_init()
1533 intel_pch_reset_handshake(display, false); in bxt_display_core_init()
1535 if (!HAS_DISPLAY(display)) in bxt_display_core_init()
1541 well = lookup_power_well(display, SKL_DISP_PW_1); in bxt_display_core_init()
1542 intel_power_well_enable(display, well); in bxt_display_core_init()
1546 intel_cdclk_init_hw(display); in bxt_display_core_init()
1548 gen9_dbuf_enable(display); in bxt_display_core_init()
1551 intel_dmc_load_program(display); in bxt_display_core_init()
1554 static void bxt_display_core_uninit(struct intel_display *display) in bxt_display_core_uninit() argument
1556 struct i915_power_domains *power_domains = &display->power.domains; in bxt_display_core_uninit()
1559 if (!HAS_DISPLAY(display)) in bxt_display_core_uninit()
1562 gen9_disable_dc_states(display); in bxt_display_core_uninit()
1565 gen9_dbuf_disable(display); in bxt_display_core_uninit()
1567 intel_cdclk_uninit_hw(display); in bxt_display_core_uninit()
1578 well = lookup_power_well(display, SKL_DISP_PW_1); in bxt_display_core_uninit()
1579 intel_power_well_disable(display, well); in bxt_display_core_uninit()
1616 static void tgl_bw_buddy_init(struct intel_display *display) in tgl_bw_buddy_init() argument
1618 const struct dram_info *dram_info = intel_dram_info(display->drm); in tgl_bw_buddy_init()
1620 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; in tgl_bw_buddy_init()
1624 if (display->platform.dgfx && !display->platform.dg1) in tgl_bw_buddy_init()
1627 if (display->platform.alderlake_s || in tgl_bw_buddy_init()
1628 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))) in tgl_bw_buddy_init()
1640 drm_dbg_kms(display->drm, in tgl_bw_buddy_init()
1643 intel_de_write(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1647 intel_de_write(display, BW_BUDDY_PAGE_MASK(i), in tgl_bw_buddy_init()
1651 if (DISPLAY_VER(display) == 12) in tgl_bw_buddy_init()
1652 intel_de_rmw(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1659 static void icl_display_core_init(struct intel_display *display, in icl_display_core_init() argument
1662 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_init()
1665 gen9_set_dc_state(display, DC_STATE_DISABLE); in icl_display_core_init()
1668 if (INTEL_PCH_TYPE(display) >= PCH_TGP && in icl_display_core_init()
1669 INTEL_PCH_TYPE(display) < PCH_DG1) in icl_display_core_init()
1670 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, in icl_display_core_init()
1674 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); in icl_display_core_init()
1676 if (!HAS_DISPLAY(display)) in icl_display_core_init()
1680 intel_combo_phy_init(display); in icl_display_core_init()
1687 well = lookup_power_well(display, SKL_DISP_PW_1); in icl_display_core_init()
1688 intel_power_well_enable(display, well); in icl_display_core_init()
1691 if (DISPLAY_VER(display) == 14) in icl_display_core_init()
1692 intel_de_rmw(display, DC_STATE_EN, in icl_display_core_init()
1696 intel_cdclk_init_hw(display); in icl_display_core_init()
1698 if (DISPLAY_VER(display) == 12 || display->platform.dg2) in icl_display_core_init()
1699 gen12_dbuf_slices_config(display); in icl_display_core_init()
1702 gen9_dbuf_enable(display); in icl_display_core_init()
1705 icl_mbus_init(display); in icl_display_core_init()
1708 if (DISPLAY_VER(display) >= 12) in icl_display_core_init()
1709 tgl_bw_buddy_init(display); in icl_display_core_init()
1712 if (display->platform.dg2) in icl_display_core_init()
1713 intel_snps_phy_wait_for_calibration(display); in icl_display_core_init()
1716 if (DISPLAY_VERx100(display) == 1401) in icl_display_core_init()
1717 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); in icl_display_core_init()
1720 intel_dmc_load_program(display); in icl_display_core_init()
1723 if (IS_DISPLAY_VERx100(display, 1200, 1300)) in icl_display_core_init()
1724 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, in icl_display_core_init()
1729 if (DISPLAY_VER(display) == 13) in icl_display_core_init()
1730 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); in icl_display_core_init()
1733 if (DISPLAY_VER(display) == 20) { in icl_display_core_init()
1734 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1736 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1741 static void icl_display_core_uninit(struct intel_display *display) in icl_display_core_uninit() argument
1743 struct i915_power_domains *power_domains = &display->power.domains; in icl_display_core_uninit()
1746 if (!HAS_DISPLAY(display)) in icl_display_core_uninit()
1749 gen9_disable_dc_states(display); in icl_display_core_uninit()
1750 intel_dmc_disable_program(display); in icl_display_core_uninit()
1752 /* 1. Disable all display engine functions -> already done */ in icl_display_core_uninit()
1755 gen9_dbuf_disable(display); in icl_display_core_uninit()
1758 intel_cdclk_uninit_hw(display); in icl_display_core_uninit()
1760 if (DISPLAY_VER(display) == 14) in icl_display_core_uninit()
1761 intel_de_rmw(display, DC_STATE_EN, 0, in icl_display_core_uninit()
1770 well = lookup_power_well(display, SKL_DISP_PW_1); in icl_display_core_uninit()
1771 intel_power_well_disable(display, well); in icl_display_core_uninit()
1775 intel_combo_phy_uninit(display); in icl_display_core_uninit()
1778 static void chv_phy_control_init(struct intel_display *display) in chv_phy_control_init() argument
1781 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in chv_phy_control_init()
1783 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); in chv_phy_control_init()
1792 display->power.chv_phy_control = in chv_phy_control_init()
1806 if (intel_power_well_is_enabled(display, cmn_bc)) { in chv_phy_control_init()
1807 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); in chv_phy_control_init()
1814 display->power.chv_phy_control |= in chv_phy_control_init()
1817 display->power.chv_phy_control |= in chv_phy_control_init()
1824 display->power.chv_phy_control |= in chv_phy_control_init()
1827 display->power.chv_phy_control |= in chv_phy_control_init()
1830 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
1832 display->power.chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
1834 display->power.chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
1837 if (intel_power_well_is_enabled(display, cmn_d)) { in chv_phy_control_init()
1838 u32 status = intel_de_read(display, DPIO_PHY_STATUS); in chv_phy_control_init()
1846 display->power.chv_phy_control |= in chv_phy_control_init()
1849 display->power.chv_phy_control |= in chv_phy_control_init()
1852 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
1854 display->power.chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
1856 display->power.chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
1859 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", in chv_phy_control_init()
1860 display->power.chv_phy_control); in chv_phy_control_init()
1865 static void vlv_cmnlane_wa(struct intel_display *display) in vlv_cmnlane_wa() argument
1868 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); in vlv_cmnlane_wa()
1870 lookup_power_well(display, VLV_DISP_PW_DISP2D); in vlv_cmnlane_wa()
1872 /* If the display might be already active skip this */ in vlv_cmnlane_wa()
1873 if (intel_power_well_is_enabled(display, cmn) && in vlv_cmnlane_wa()
1874 intel_power_well_is_enabled(display, disp2d) && in vlv_cmnlane_wa()
1875 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) in vlv_cmnlane_wa()
1878 drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); in vlv_cmnlane_wa()
1881 intel_power_well_enable(display, disp2d); in vlv_cmnlane_wa()
1890 intel_power_well_disable(display, cmn); in vlv_cmnlane_wa()
1893 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) in vlv_punit_is_power_gated() argument
1897 vlv_punit_get(display->drm); in vlv_punit_is_power_gated()
1898 ret = (vlv_punit_read(display->drm, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; in vlv_punit_is_power_gated()
1899 vlv_punit_put(display->drm); in vlv_punit_is_power_gated()
1904 static void assert_ved_power_gated(struct intel_display *display) in assert_ved_power_gated() argument
1906 drm_WARN(display->drm, in assert_ved_power_gated()
1907 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), in assert_ved_power_gated()
1911 static void assert_isp_power_gated(struct intel_display *display) in assert_isp_power_gated() argument
1919 drm_WARN(display->drm, !pci_dev_present(isp_ids) && in assert_isp_power_gated()
1920 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), in assert_isp_power_gated()
1924 static void intel_power_domains_verify_state(struct intel_display *display);
1928 * @display: display device instance
1942 void intel_power_domains_init_hw(struct intel_display *display, bool resume) in intel_power_domains_init_hw() argument
1944 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_init_hw()
1948 if (DISPLAY_VER(display) >= 11) { in intel_power_domains_init_hw()
1949 icl_display_core_init(display, resume); in intel_power_domains_init_hw()
1950 } else if (display->platform.geminilake || display->platform.broxton) { in intel_power_domains_init_hw()
1951 bxt_display_core_init(display, resume); in intel_power_domains_init_hw()
1952 } else if (DISPLAY_VER(display) == 9) { in intel_power_domains_init_hw()
1953 skl_display_core_init(display, resume); in intel_power_domains_init_hw()
1954 } else if (display->platform.cherryview) { in intel_power_domains_init_hw()
1956 chv_phy_control_init(display); in intel_power_domains_init_hw()
1958 assert_isp_power_gated(display); in intel_power_domains_init_hw()
1959 } else if (display->platform.valleyview) { in intel_power_domains_init_hw()
1961 vlv_cmnlane_wa(display); in intel_power_domains_init_hw()
1963 assert_ved_power_gated(display); in intel_power_domains_init_hw()
1964 assert_isp_power_gated(display); in intel_power_domains_init_hw()
1965 } else if (display->platform.broadwell || display->platform.haswell) { in intel_power_domains_init_hw()
1966 hsw_assert_cdclk(display); in intel_power_domains_init_hw()
1967 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); in intel_power_domains_init_hw()
1968 } else if (display->platform.ivybridge) { in intel_power_domains_init_hw()
1969 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display)); in intel_power_domains_init_hw()
1974 * initialization and to make sure we keep BIOS enabled display HW in intel_power_domains_init_hw()
1975 * resources powered until display HW readout is complete. We drop in intel_power_domains_init_hw()
1978 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_init_hw()
1980 intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_power_domains_init_hw()
1983 if (!display->params.disable_power_well) { in intel_power_domains_init_hw()
1984 drm_WARN_ON(display->drm, power_domains->disable_wakeref); in intel_power_domains_init_hw()
1985 display->power.domains.disable_wakeref = intel_display_power_get(display, in intel_power_domains_init_hw()
1988 intel_power_domains_sync_hw(display); in intel_power_domains_init_hw()
1995 * @display: display device instance
1997 * De-initializes the display power domain HW state. It also ensures that the
2004 void intel_power_domains_driver_remove(struct intel_display *display) in intel_power_domains_driver_remove() argument
2007 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_driver_remove()
2010 if (!display->params.disable_power_well) in intel_power_domains_driver_remove()
2011 intel_display_power_put(display, POWER_DOMAIN_INIT, in intel_power_domains_driver_remove()
2012 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_driver_remove()
2014 intel_display_power_flush_work_sync(display); in intel_power_domains_driver_remove()
2016 intel_power_domains_verify_state(display); in intel_power_domains_driver_remove()
2019 intel_display_rpm_put(display, wakeref); in intel_power_domains_driver_remove()
2024 * @display: display device instance
2027 * The function will disable all display power wells that BIOS has enabled
2032 void intel_power_domains_sanitize_state(struct intel_display *display) in intel_power_domains_sanitize_state() argument
2034 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_sanitize_state()
2039 for_each_power_well_reverse(display, power_well) { in intel_power_domains_sanitize_state()
2041 !intel_power_well_is_enabled(display, power_well)) in intel_power_domains_sanitize_state()
2044 drm_dbg_kms(display->drm, in intel_power_domains_sanitize_state()
2047 intel_power_well_disable(display, power_well); in intel_power_domains_sanitize_state()
2054 * intel_power_domains_enable - enable toggling of display power wells
2055 * @display: display device instance
2057 * Enable the ondemand enabling/disabling of the display power wells. Note that
2059 * only at specific points of the display modeset sequence, thus they are not
2062 * of display HW readout (which will acquire the power references reflecting
2065 void intel_power_domains_enable(struct intel_display *display) in intel_power_domains_enable() argument
2068 fetch_and_zero(&display->power.domains.init_wakeref); in intel_power_domains_enable()
2070 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); in intel_power_domains_enable()
2071 intel_power_domains_verify_state(display); in intel_power_domains_enable()
2075 * intel_power_domains_disable - disable toggling of display power wells
2076 * @display: display device instance
2078 * Disable the ondemand enabling/disabling of the display power wells. See
2081 void intel_power_domains_disable(struct intel_display *display) in intel_power_domains_disable() argument
2083 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_disable()
2085 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_disable()
2087 intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_power_domains_disable()
2089 intel_power_domains_verify_state(display); in intel_power_domains_disable()
2094 * @display: display device instance
2103 void intel_power_domains_suspend(struct intel_display *display, bool s2idle) in intel_power_domains_suspend() argument
2105 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_suspend()
2109 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); in intel_power_domains_suspend()
2119 intel_dmc_has_payload(display)) { in intel_power_domains_suspend()
2120 intel_display_power_flush_work(display); in intel_power_domains_suspend()
2121 intel_power_domains_verify_state(display); in intel_power_domains_suspend()
2129 if (!display->params.disable_power_well) in intel_power_domains_suspend()
2130 intel_display_power_put(display, POWER_DOMAIN_INIT, in intel_power_domains_suspend()
2131 fetch_and_zero(&display->power.domains.disable_wakeref)); in intel_power_domains_suspend()
2133 intel_display_power_flush_work(display); in intel_power_domains_suspend()
2134 intel_power_domains_verify_state(display); in intel_power_domains_suspend()
2136 if (DISPLAY_VER(display) >= 11) in intel_power_domains_suspend()
2137 icl_display_core_uninit(display); in intel_power_domains_suspend()
2138 else if (display->platform.geminilake || display->platform.broxton) in intel_power_domains_suspend()
2139 bxt_display_core_uninit(display); in intel_power_domains_suspend()
2140 else if (DISPLAY_VER(display) == 9) in intel_power_domains_suspend()
2141 skl_display_core_uninit(display); in intel_power_domains_suspend()
2148 * @display: display device instance
2156 void intel_power_domains_resume(struct intel_display *display) in intel_power_domains_resume() argument
2158 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_resume()
2161 intel_power_domains_init_hw(display, true); in intel_power_domains_resume()
2164 drm_WARN_ON(display->drm, power_domains->init_wakeref); in intel_power_domains_resume()
2166 intel_display_power_get(display, POWER_DOMAIN_INIT); in intel_power_domains_resume()
2172 static void intel_power_domains_dump_info(struct intel_display *display) in intel_power_domains_dump_info() argument
2174 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_dump_info()
2177 for_each_power_well(display, power_well) { in intel_power_domains_dump_info()
2180 drm_dbg_kms(display->drm, "%-25s %d\n", in intel_power_domains_dump_info()
2184 drm_dbg_kms(display->drm, " %-23s %d\n", in intel_power_domains_dump_info()
2192 * @display: display device instance
2200 static void intel_power_domains_verify_state(struct intel_display *display) in intel_power_domains_verify_state() argument
2202 struct i915_power_domains *power_domains = &display->power.domains; in intel_power_domains_verify_state()
2211 for_each_power_well(display, power_well) { in intel_power_domains_verify_state()
2216 enabled = intel_power_well_is_enabled(display, power_well); in intel_power_domains_verify_state()
2220 drm_err(display->drm, in intel_power_domains_verify_state()
2230 drm_err(display->drm, in intel_power_domains_verify_state()
2244 intel_power_domains_dump_info(display); in intel_power_domains_verify_state()
2254 static void intel_power_domains_verify_state(struct intel_display *display) in intel_power_domains_verify_state() argument
2260 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) in intel_display_power_suspend_late() argument
2262 intel_power_domains_suspend(display, s2idle); in intel_display_power_suspend_late()
2264 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_suspend_late()
2265 display->platform.broxton) { in intel_display_power_suspend_late()
2266 bxt_enable_dc9(display); in intel_display_power_suspend_late()
2267 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend_late()
2268 hsw_enable_pc8(display); in intel_display_power_suspend_late()
2272 if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1) in intel_display_power_suspend_late()
2273 intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); in intel_display_power_suspend_late()
2276 void intel_display_power_resume_early(struct intel_display *display) in intel_display_power_resume_early() argument
2278 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_resume_early()
2279 display->platform.broxton) { in intel_display_power_resume_early()
2280 gen9_sanitize_dc_state(display); in intel_display_power_resume_early()
2281 bxt_disable_dc9(display); in intel_display_power_resume_early()
2282 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume_early()
2283 hsw_disable_pc8(display); in intel_display_power_resume_early()
2287 if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1) in intel_display_power_resume_early()
2288 intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); in intel_display_power_resume_early()
2290 intel_power_domains_resume(display); in intel_display_power_resume_early()
2293 void intel_display_power_suspend(struct intel_display *display) in intel_display_power_suspend() argument
2295 if (DISPLAY_VER(display) >= 11) { in intel_display_power_suspend()
2296 icl_display_core_uninit(display); in intel_display_power_suspend()
2297 bxt_enable_dc9(display); in intel_display_power_suspend()
2298 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_suspend()
2299 bxt_display_core_uninit(display); in intel_display_power_suspend()
2300 bxt_enable_dc9(display); in intel_display_power_suspend()
2301 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_suspend()
2302 hsw_enable_pc8(display); in intel_display_power_suspend()
2306 void intel_display_power_resume(struct intel_display *display) in intel_display_power_resume() argument
2308 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_resume()
2310 if (DISPLAY_VER(display) >= 11) { in intel_display_power_resume()
2311 bxt_disable_dc9(display); in intel_display_power_resume()
2312 icl_display_core_init(display, true); in intel_display_power_resume()
2313 if (intel_dmc_has_payload(display)) { in intel_display_power_resume()
2315 skl_enable_dc6(display); in intel_display_power_resume()
2317 gen9_enable_dc5(display); in intel_display_power_resume()
2319 } else if (display->platform.geminilake || display->platform.broxton) { in intel_display_power_resume()
2320 bxt_disable_dc9(display); in intel_display_power_resume()
2321 bxt_display_core_init(display, true); in intel_display_power_resume()
2322 if (intel_dmc_has_payload(display) && in intel_display_power_resume()
2324 gen9_enable_dc5(display); in intel_display_power_resume()
2325 } else if (display->platform.haswell || display->platform.broadwell) { in intel_display_power_resume()
2326 hsw_disable_pc8(display); in intel_display_power_resume()
2330 void intel_display_power_debug(struct intel_display *display, struct seq_file *m) in intel_display_power_debug() argument
2332 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_debug()
2480 intel_port_domains_for_platform(struct intel_display *display, in intel_port_domains_for_platform() argument
2484 if (DISPLAY_VER(display) >= 13) { in intel_port_domains_for_platform()
2487 } else if (DISPLAY_VER(display) >= 12) { in intel_port_domains_for_platform()
2490 } else if (DISPLAY_VER(display) >= 11) { in intel_port_domains_for_platform()
2500 intel_port_domains_for_port(struct intel_display *display, enum port port) in intel_port_domains_for_port() argument
2506 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_port()
2515 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port) in intel_display_power_ddi_io_domain() argument
2517 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_io_domain()
2519 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_io_domain()
2526 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port) in intel_display_power_ddi_lanes_domain() argument
2528 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); in intel_display_power_ddi_lanes_domain()
2530 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) in intel_display_power_ddi_lanes_domain()
2537 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) in intel_port_domains_for_aux_ch() argument
2543 intel_port_domains_for_platform(display, &domains, &domains_size); in intel_port_domains_for_aux_ch()
2552 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch) in intel_display_power_aux_io_domain() argument
2554 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_aux_io_domain()
2556 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) in intel_display_power_aux_io_domain()
2563 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch) in intel_display_power_legacy_aux_domain() argument
2565 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_legacy_aux_domain()
2567 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) in intel_display_power_legacy_aux_domain()
2574 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch) in intel_display_power_tbt_aux_domain() argument
2576 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); in intel_display_power_tbt_aux_domain()
2578 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) in intel_display_power_tbt_aux_domain()