Lines Matching defs:display
202 static bool __intel_display_power_is_enabled(struct intel_display *display,
208 if (intel_display_rpm_suspended(display))
213 for_each_power_domain_well_reverse(display, power_well, domain) {
228 * @display: display device instance
243 bool intel_display_power_is_enabled(struct intel_display *display,
246 struct i915_power_domains *power_domains = &display->power.domains;
250 ret = __intel_display_power_is_enabled(display, domain);
257 sanitize_target_dc_state(struct intel_display *display,
260 struct i915_power_domains *power_domains = &display->power.domains;
284 * @display: display device
291 void intel_display_power_set_target_dc_state(struct intel_display *display,
296 struct i915_power_domains *power_domains = &display->power.domains;
299 power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
301 if (drm_WARN_ON(display->drm, !power_well))
304 state = sanitize_target_dc_state(display, state);
309 dc_off_enabled = intel_power_well_is_enabled(display, power_well);
315 intel_power_well_enable(display, power_well);
320 intel_power_well_disable(display, power_well);
328 * @display: display device
334 u32 intel_display_power_get_current_dc_state(struct intel_display *display)
337 struct i915_power_domains *power_domains = &display->power.domains;
341 power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
343 if (drm_WARN_ON(display->drm, !power_well))
346 current_dc_state = intel_power_well_is_enabled(display, power_well) ?
369 struct intel_display *display = container_of(power_domains,
373 return !drm_WARN_ON(display->drm,
382 struct intel_display *display = container_of(power_domains,
391 err |= drm_WARN_ON(display->drm,
396 err |= drm_WARN_ON(display->drm,
405 struct intel_display *display = container_of(power_domains,
410 drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
412 drm_dbg_kms(display->drm, "%s use_count %d\n",
420 struct intel_display *display = container_of(power_domains,
424 drm_dbg_kms(display->drm, "async_put_wakeref: %s\n",
485 intel_display_power_grab_async_put_ref(struct intel_display *display,
488 struct i915_power_domains *power_domains = &display->power.domains;
505 intel_display_rpm_put_raw(display,
514 __intel_display_power_get_domain(struct intel_display *display,
517 struct i915_power_domains *power_domains = &display->power.domains;
520 if (intel_display_power_grab_async_put_ref(display, domain))
523 for_each_power_domain_well(display, power_well, domain)
524 intel_power_well_get(display, power_well);
531 * @display: display device instance
541 intel_wakeref_t intel_display_power_get(struct intel_display *display,
544 struct i915_power_domains *power_domains = &display->power.domains;
547 wakeref = intel_display_rpm_get(display);
550 __intel_display_power_get_domain(display, domain);
557 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
558 * @display: display device instance
569 intel_display_power_get_if_enabled(struct intel_display *display,
572 struct i915_power_domains *power_domains = &display->power.domains;
576 wakeref = intel_display_rpm_get_if_in_use(display);
582 if (__intel_display_power_is_enabled(display, domain)) {
583 __intel_display_power_get_domain(display, domain);
592 intel_display_rpm_put(display, wakeref);
600 __intel_display_power_put_domain(struct intel_display *display,
603 struct i915_power_domains *power_domains = &display->power.domains;
608 drm_WARN(display->drm, !power_domains->domain_use_count[domain],
612 drm_WARN(display->drm,
619 for_each_power_domain_well_reverse(display, power_well, domain)
620 intel_power_well_put(display, power_well);
623 static void __intel_display_power_put(struct intel_display *display,
626 struct i915_power_domains *power_domains = &display->power.domains;
629 __intel_display_power_put_domain(display, domain);
638 struct intel_display *display = container_of(power_domains,
641 drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
643 drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq,
652 struct intel_display *display = container_of(power_domains,
658 wakeref = intel_display_rpm_get_noresume(display);
663 __intel_display_power_put_domain(display, domain);
666 intel_display_rpm_put(display, wakeref);
672 struct intel_display *display = container_of(work, struct intel_display,
674 struct i915_power_domains *power_domains = &display->power.domains;
677 new_work_wakeref = intel_display_rpm_get_raw(display);
717 intel_display_rpm_put_raw(display, old_work_wakeref);
719 intel_display_rpm_put_raw(display, new_work_wakeref);
724 * @display: display device instance
735 void __intel_display_power_put_async(struct intel_display *display,
740 struct i915_power_domains *power_domains = &display->power.domains;
743 work_wakeref = intel_display_rpm_get_raw(display);
750 __intel_display_power_put_domain(display, domain);
755 drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1);
775 intel_display_rpm_put_raw(display, work_wakeref);
777 intel_display_rpm_put(display, wakeref);
781 * intel_display_power_flush_work - flushes the async display power disabling work
782 * @display: display device instance
792 void intel_display_power_flush_work(struct intel_display *display)
794 struct i915_power_domains *power_domains = &display->power.domains;
814 intel_display_rpm_put_raw(display, work_wakeref);
818 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work
819 * @display: display device instance
825 intel_display_power_flush_work_sync(struct intel_display *display)
827 struct i915_power_domains *power_domains = &display->power.domains;
829 intel_display_power_flush_work(display);
834 drm_WARN_ON(display->drm, power_domains->async_put_wakeref);
840 * @display: display device instance
848 void intel_display_power_put(struct intel_display *display,
852 __intel_display_power_put(display, domain);
853 intel_display_rpm_put(display, wakeref);
858 * @display: display device instance
869 void intel_display_power_put_unchecked(struct intel_display *display,
872 __intel_display_power_put(display, domain);
873 intel_display_rpm_put_unchecked(display);
878 intel_display_power_get_in_set(struct intel_display *display,
884 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
886 wf = intel_display_power_get(display, domain);
894 intel_display_power_get_in_set_if_enabled(struct intel_display *display,
900 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits));
902 wf = intel_display_power_get_if_enabled(display, domain);
915 intel_display_power_put_mask_in_set(struct intel_display *display,
921 drm_WARN_ON(display->drm,
930 intel_display_power_put(display, domain, wf);
944 static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
950 if (!HAS_DISPLAY(display))
953 if (DISPLAY_VER(display) >= 20)
955 else if (display->platform.dg2)
957 else if (display->platform.dg1)
959 else if (DISPLAY_VER(display) >= 12)
961 else if (display->platform.geminilake || display->platform.broxton)
963 else if (DISPLAY_VER(display) >= 9)
973 mask = display->platform.geminilake || display->platform.broxton ||
974 DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0;
976 if (!display->params.disable_power_well)
984 drm_dbg_kms(display->drm,
989 drm_err(display->drm,
1009 drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask);
1016 * @display: display device instance
1018 * Initializes the power domain structures for @display depending upon the
1021 int intel_power_domains_init(struct intel_display *display)
1023 struct i915_power_domains *power_domains = &display->power.domains;
1025 display->params.disable_power_well =
1026 sanitize_disable_power_well_option(display->params.disable_power_well);
1028 get_allowed_dc_mask(display, display->params.enable_dc);
1031 sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
1043 * @display: display device instance
1047 void intel_power_domains_cleanup(struct intel_display *display)
1049 intel_display_power_map_cleanup(&display->power.domains);
1052 static void intel_power_domains_sync_hw(struct intel_display *display)
1054 struct i915_power_domains *power_domains = &display->power.domains;
1058 for_each_power_well(display, power_well)
1059 intel_power_well_sync_hw(display, power_well);
1063 static void gen9_dbuf_slice_set(struct intel_display *display,
1069 intel_de_rmw(display, reg, DBUF_POWER_REQUEST,
1071 intel_de_posting_read(display, reg);
1074 state = intel_de_read(display, reg) & DBUF_POWER_STATE;
1075 drm_WARN(display->drm, enable != state,
1080 void gen9_dbuf_slices_update(struct intel_display *display,
1083 struct i915_power_domains *power_domains = &display->power.domains;
1084 u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask;
1087 drm_WARN(display->drm, req_slices & ~slice_mask,
1091 drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n",
1103 for_each_dbuf_slice(display, slice)
1104 gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice));
1106 display->dbuf.enabled_slices = req_slices;
1111 static void gen9_dbuf_enable(struct intel_display *display)
1115 display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display);
1117 slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices;
1119 if (DISPLAY_VER(display) >= 14)
1120 intel_pmdemand_program_dbuf(display, slices_mask);
1126 gen9_dbuf_slices_update(display, slices_mask);
1129 static void gen9_dbuf_disable(struct intel_display *display)
1131 gen9_dbuf_slices_update(display, 0);
1133 if (DISPLAY_VER(display) >= 14)
1134 intel_pmdemand_program_dbuf(display, 0);
1137 static void gen12_dbuf_slices_config(struct intel_display *display)
1141 for_each_dbuf_slice(display, slice)
1142 intel_de_rmw(display, DBUF_CTL_S(slice),
1147 static void icl_mbus_init(struct intel_display *display)
1149 unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask;
1152 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
1169 if (DISPLAY_VER(display) == 12)
1173 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val);
1176 static void hsw_assert_cdclk(struct intel_display *display)
1178 u32 val = intel_de_read(display, LCPLL_CTL);
1187 drm_err(display->drm, "CDCLK source is not LCPLL\n");
1190 drm_err(display->drm, "LCPLL is disabled\n");
1193 drm_err(display->drm, "LCPLL not using non-SSC reference\n");
1196 static void assert_can_disable_lcpll(struct intel_display *display)
1198 struct drm_i915_private *dev_priv = to_i915(display->drm);
1201 for_each_intel_crtc(display->drm, crtc)
1202 INTEL_DISPLAY_STATE_WARN(display, crtc->active,
1206 INTEL_DISPLAY_STATE_WARN(display, intel_de_read(display, HSW_PWR_WELL_CTL2),
1208 INTEL_DISPLAY_STATE_WARN(display,
1209 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE,
1211 INTEL_DISPLAY_STATE_WARN(display,
1212 intel_de_read(display, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
1214 INTEL_DISPLAY_STATE_WARN(display,
1215 intel_de_read(display, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
1217 INTEL_DISPLAY_STATE_WARN(display,
1218 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON,
1220 INTEL_DISPLAY_STATE_WARN(display,
1221 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
1223 if (display->platform.haswell)
1224 INTEL_DISPLAY_STATE_WARN(display,
1225 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
1227 INTEL_DISPLAY_STATE_WARN(display,
1228 intel_de_read(display, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
1230 INTEL_DISPLAY_STATE_WARN(display,
1231 (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM),
1233 INTEL_DISPLAY_STATE_WARN(display,
1234 intel_de_read(display, PCH_GTC_CTL) & PCH_GTC_ENABLE,
1243 INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv),
1247 static u32 hsw_read_dcomp(struct intel_display *display)
1249 if (display->platform.haswell)
1250 return intel_de_read(display, D_COMP_HSW);
1252 return intel_de_read(display, D_COMP_BDW);
1255 static void hsw_write_dcomp(struct intel_display *display, u32 val)
1257 struct drm_i915_private *dev_priv = to_i915(display->drm);
1259 if (display->platform.haswell) {
1261 drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");
1263 intel_de_write(display, D_COMP_BDW, val);
1264 intel_de_posting_read(display, D_COMP_BDW);
1270 * - Sequence for display software to disable LCPLL
1271 * - Sequence for display software to allow package C8+
1273 * register. Callers should take care of disabling all the display engine
1276 static void hsw_disable_lcpll(struct intel_display *display,
1281 assert_can_disable_lcpll(display);
1283 val = intel_de_read(display, LCPLL_CTL);
1287 intel_de_write(display, LCPLL_CTL, val);
1289 if (wait_for_us(intel_de_read(display, LCPLL_CTL) &
1291 drm_err(display->drm, "Switching to FCLK failed\n");
1293 val = intel_de_read(display, LCPLL_CTL);
1297 intel_de_write(display, LCPLL_CTL, val);
1298 intel_de_posting_read(display, LCPLL_CTL);
1300 if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
1301 drm_err(display->drm, "LCPLL still locked\n");
1303 val = hsw_read_dcomp(display);
1305 hsw_write_dcomp(display, val);
1308 if (wait_for((hsw_read_dcomp(display) &
1310 drm_err(display->drm, "D_COMP RCOMP still in progress\n");
1313 intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW);
1314 intel_de_posting_read(display, LCPLL_CTL);
1322 static void hsw_restore_lcpll(struct intel_display *display)
1324 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
1327 val = intel_de_read(display, LCPLL_CTL);
1341 intel_de_write(display, LCPLL_CTL, val);
1342 intel_de_posting_read(display, LCPLL_CTL);
1345 val = hsw_read_dcomp(display);
1348 hsw_write_dcomp(display, val);
1350 val = intel_de_read(display, LCPLL_CTL);
1352 intel_de_write(display, LCPLL_CTL, val);
1354 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
1355 drm_err(display->drm, "LCPLL not locked yet\n");
1358 intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
1360 if (wait_for_us((intel_de_read(display, LCPLL_CTL) &
1362 drm_err(display->drm,
1368 intel_update_cdclk(display);
1369 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
1395 static void hsw_enable_pc8(struct intel_display *display)
1397 drm_dbg_kms(display->drm, "Enabling package C8+\n");
1399 if (HAS_PCH_LPT_LP(display))
1400 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1403 lpt_disable_clkout_dp(display);
1404 hsw_disable_lcpll(display, true, true);
1407 static void hsw_disable_pc8(struct intel_display *display)
1409 struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm);
1411 drm_dbg_kms(display->drm, "Disabling package C8+\n");
1413 hsw_restore_lcpll(display);
1414 intel_init_pch_refclk(display);
1416 /* Many display registers don't survive PC8+ */
1422 static void intel_pch_reset_handshake(struct intel_display *display,
1428 if (display->platform.ivybridge) {
1436 if (DISPLAY_VER(display) >= 14)
1439 intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0);
1442 static void skl_display_core_init(struct intel_display *display,
1445 struct i915_power_domains *power_domains = &display->power.domains;
1448 gen9_set_dc_state(display, DC_STATE_DISABLE);
1451 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
1453 if (!HAS_DISPLAY(display))
1459 well = lookup_power_well(display, SKL_DISP_PW_1);
1460 intel_power_well_enable(display, well);
1462 well = lookup_power_well(display, SKL_DISP_PW_MISC_IO);
1463 intel_power_well_enable(display, well);
1467 intel_cdclk_init_hw(display);
1469 gen9_dbuf_enable(display);
1472 intel_dmc_load_program(display);
1475 static void skl_display_core_uninit(struct intel_display *display)
1477 struct i915_power_domains *power_domains = &display->power.domains;
1480 if (!HAS_DISPLAY(display))
1483 gen9_disable_dc_states(display);
1486 gen9_dbuf_disable(display);
1488 intel_cdclk_uninit_hw(display);
1501 well = lookup_power_well(display, SKL_DISP_PW_1);
1502 intel_power_well_disable(display, well);
1509 static void bxt_display_core_init(struct intel_display *display, bool resume)
1511 struct i915_power_domains *power_domains = &display->power.domains;
1514 gen9_set_dc_state(display, DC_STATE_DISABLE);
1522 intel_pch_reset_handshake(display, false);
1524 if (!HAS_DISPLAY(display))
1530 well = lookup_power_well(display, SKL_DISP_PW_1);
1531 intel_power_well_enable(display, well);
1535 intel_cdclk_init_hw(display);
1537 gen9_dbuf_enable(display);
1540 intel_dmc_load_program(display);
1543 static void bxt_display_core_uninit(struct intel_display *display)
1545 struct i915_power_domains *power_domains = &display->power.domains;
1548 if (!HAS_DISPLAY(display))
1551 gen9_disable_dc_states(display);
1554 gen9_dbuf_disable(display);
1556 intel_cdclk_uninit_hw(display);
1567 well = lookup_power_well(display, SKL_DISP_PW_1);
1568 intel_power_well_disable(display, well);
1605 static void tgl_bw_buddy_init(struct intel_display *display)
1607 struct drm_i915_private *dev_priv = to_i915(display->drm);
1611 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;
1615 if (display->platform.dgfx && !display->platform.dg1)
1618 if (display->platform.alderlake_s ||
1619 (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)))
1631 drm_dbg_kms(display->drm,
1634 intel_de_write(display, BW_BUDDY_CTL(i),
1638 intel_de_write(display, BW_BUDDY_PAGE_MASK(i),
1642 if (DISPLAY_VER(display) == 12)
1643 intel_de_rmw(display, BW_BUDDY_CTL(i),
1650 static void icl_display_core_init(struct intel_display *display,
1653 struct i915_power_domains *power_domains = &display->power.domains;
1656 gen9_set_dc_state(display, DC_STATE_DISABLE);
1659 if (INTEL_PCH_TYPE(display) >= PCH_TGP &&
1660 INTEL_PCH_TYPE(display) < PCH_DG1)
1661 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0,
1665 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
1667 if (!HAS_DISPLAY(display))
1671 intel_combo_phy_init(display);
1678 well = lookup_power_well(display, SKL_DISP_PW_1);
1679 intel_power_well_enable(display, well);
1682 if (DISPLAY_VER(display) == 14)
1683 intel_de_rmw(display, DC_STATE_EN,
1687 intel_cdclk_init_hw(display);
1689 if (DISPLAY_VER(display) == 12 || display->platform.dg2)
1690 gen12_dbuf_slices_config(display);
1693 gen9_dbuf_enable(display);
1696 icl_mbus_init(display);
1699 if (DISPLAY_VER(display) >= 12)
1700 tgl_bw_buddy_init(display);
1703 if (display->platform.dg2)
1704 intel_snps_phy_wait_for_calibration(display);
1707 if (DISPLAY_VERx100(display) == 1401)
1708 intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1);
1711 intel_dmc_load_program(display);
1714 if (IS_DISPLAY_VERx100(display, 1200, 1300))
1715 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0,
1720 if (DISPLAY_VER(display) == 13)
1721 intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
1724 if (DISPLAY_VER(display) == 20) {
1725 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1727 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
1732 static void icl_display_core_uninit(struct intel_display *display)
1734 struct i915_power_domains *power_domains = &display->power.domains;
1737 if (!HAS_DISPLAY(display))
1740 gen9_disable_dc_states(display);
1741 intel_dmc_disable_program(display);
1743 /* 1. Disable all display engine functions -> already done */
1746 gen9_dbuf_disable(display);
1749 intel_cdclk_uninit_hw(display);
1751 if (DISPLAY_VER(display) == 14)
1752 intel_de_rmw(display, DC_STATE_EN, 0,
1761 well = lookup_power_well(display, SKL_DISP_PW_1);
1762 intel_power_well_disable(display, well);
1766 intel_combo_phy_uninit(display);
1769 static void chv_phy_control_init(struct intel_display *display)
1772 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
1774 lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D);
1783 display->power.chv_phy_control =
1797 if (intel_power_well_is_enabled(display, cmn_bc)) {
1798 u32 status = intel_de_read(display, DPLL(display, PIPE_A));
1805 display->power.chv_phy_control |=
1808 display->power.chv_phy_control |=
1815 display->power.chv_phy_control |=
1818 display->power.chv_phy_control |=
1821 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1823 display->power.chv_phy_assert[DPIO_PHY0] = false;
1825 display->power.chv_phy_assert[DPIO_PHY0] = true;
1828 if (intel_power_well_is_enabled(display, cmn_d)) {
1829 u32 status = intel_de_read(display, DPIO_PHY_STATUS);
1837 display->power.chv_phy_control |=
1840 display->power.chv_phy_control |=
1843 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1845 display->power.chv_phy_assert[DPIO_PHY1] = false;
1847 display->power.chv_phy_assert[DPIO_PHY1] = true;
1850 drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n",
1851 display->power.chv_phy_control);
1856 static void vlv_cmnlane_wa(struct intel_display *display)
1859 lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC);
1861 lookup_power_well(display, VLV_DISP_PW_DISP2D);
1863 /* If the display might be already active skip this */
1864 if (intel_power_well_is_enabled(display, cmn) &&
1865 intel_power_well_is_enabled(display, disp2d) &&
1866 intel_de_read(display, DPIO_CTL) & DPIO_CMNRST)
1869 drm_dbg_kms(display->drm, "toggling display PHY side reset\n");
1872 intel_power_well_enable(display, disp2d);
1881 intel_power_well_disable(display, cmn);
1884 static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0)
1886 struct drm_i915_private *dev_priv = to_i915(display->drm);
1896 static void assert_ved_power_gated(struct intel_display *display)
1898 drm_WARN(display->drm,
1899 !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0),
1903 static void assert_isp_power_gated(struct intel_display *display)
1911 drm_WARN(display->drm, !pci_dev_present(isp_ids) &&
1912 !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0),
1916 static void intel_power_domains_verify_state(struct intel_display *display);
1920 * @display: display device instance
1934 void intel_power_domains_init_hw(struct intel_display *display, bool resume)
1936 struct i915_power_domains *power_domains = &display->power.domains;
1940 if (DISPLAY_VER(display) >= 11) {
1941 icl_display_core_init(display, resume);
1942 } else if (display->platform.geminilake || display->platform.broxton) {
1943 bxt_display_core_init(display, resume);
1944 } else if (DISPLAY_VER(display) == 9) {
1945 skl_display_core_init(display, resume);
1946 } else if (display->platform.cherryview) {
1948 chv_phy_control_init(display);
1950 assert_isp_power_gated(display);
1951 } else if (display->platform.valleyview) {
1953 vlv_cmnlane_wa(display);
1955 assert_ved_power_gated(display);
1956 assert_isp_power_gated(display);
1957 } else if (display->platform.broadwell || display->platform.haswell) {
1958 hsw_assert_cdclk(display);
1959 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
1960 } else if (display->platform.ivybridge) {
1961 intel_pch_reset_handshake(display, !HAS_PCH_NOP(display));
1966 * initialization and to make sure we keep BIOS enabled display HW
1967 * resources powered until display HW readout is complete. We drop
1970 drm_WARN_ON(display->drm, power_domains->init_wakeref);
1972 intel_display_power_get(display, POWER_DOMAIN_INIT);
1975 if (!display->params.disable_power_well) {
1976 drm_WARN_ON(display->drm, power_domains->disable_wakeref);
1977 display->power.domains.disable_wakeref = intel_display_power_get(display,
1980 intel_power_domains_sync_hw(display);
1987 * @display: display device instance
1989 * De-initializes the display power domain HW state. It also ensures that the
1996 void intel_power_domains_driver_remove(struct intel_display *display)
1999 fetch_and_zero(&display->power.domains.init_wakeref);
2002 if (!display->params.disable_power_well)
2003 intel_display_power_put(display, POWER_DOMAIN_INIT,
2004 fetch_and_zero(&display->power.domains.disable_wakeref));
2006 intel_display_power_flush_work_sync(display);
2008 intel_power_domains_verify_state(display);
2011 intel_display_rpm_put(display, wakeref);
2016 * @display: display device instance
2019 * The function will disable all display power wells that BIOS has enabled
2024 void intel_power_domains_sanitize_state(struct intel_display *display)
2026 struct i915_power_domains *power_domains = &display->power.domains;
2031 for_each_power_well_reverse(display, power_well) {
2033 !intel_power_well_is_enabled(display, power_well))
2036 drm_dbg_kms(display->drm,
2039 intel_power_well_disable(display, power_well);
2046 * intel_power_domains_enable - enable toggling of display power wells
2047 * @display: display device instance
2049 * Enable the ondemand enabling/disabling of the display power wells. Note that
2051 * only at specific points of the display modeset sequence, thus they are not
2054 * of display HW readout (which will acquire the power references reflecting
2057 void intel_power_domains_enable(struct intel_display *display)
2060 fetch_and_zero(&display->power.domains.init_wakeref);
2062 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
2063 intel_power_domains_verify_state(display);
2067 * intel_power_domains_disable - disable toggling of display power wells
2068 * @display: display device instance
2070 * Disable the ondemand enabling/disabling of the display power wells. See
2073 void intel_power_domains_disable(struct intel_display *display)
2075 struct i915_power_domains *power_domains = &display->power.domains;
2077 drm_WARN_ON(display->drm, power_domains->init_wakeref);
2079 intel_display_power_get(display, POWER_DOMAIN_INIT);
2081 intel_power_domains_verify_state(display);
2086 * @display: display device instance
2095 void intel_power_domains_suspend(struct intel_display *display, bool s2idle)
2097 struct i915_power_domains *power_domains = &display->power.domains;
2101 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
2111 intel_dmc_has_payload(display)) {
2112 intel_display_power_flush_work(display);
2113 intel_power_domains_verify_state(display);
2121 if (!display->params.disable_power_well)
2122 intel_display_power_put(display, POWER_DOMAIN_INIT,
2123 fetch_and_zero(&display->power.domains.disable_wakeref));
2125 intel_display_power_flush_work(display);
2126 intel_power_domains_verify_state(display);
2128 if (DISPLAY_VER(display) >= 11)
2129 icl_display_core_uninit(display);
2130 else if (display->platform.geminilake || display->platform.broxton)
2131 bxt_display_core_uninit(display);
2132 else if (DISPLAY_VER(display) == 9)
2133 skl_display_core_uninit(display);
2140 * @display: display device instance
2148 void intel_power_domains_resume(struct intel_display *display)
2150 struct i915_power_domains *power_domains = &display->power.domains;
2153 intel_power_domains_init_hw(display, true);
2156 drm_WARN_ON(display->drm, power_domains->init_wakeref);
2158 intel_display_power_get(display, POWER_DOMAIN_INIT);
2161 intel_power_domains_verify_state(display);
2166 static void intel_power_domains_dump_info(struct intel_display *display)
2168 struct i915_power_domains *power_domains = &display->power.domains;
2171 for_each_power_well(display, power_well) {
2174 drm_dbg_kms(display->drm, "%-25s %d\n",
2178 drm_dbg_kms(display->drm, " %-23s %d\n",
2186 * @display: display device instance
2194 static void intel_power_domains_verify_state(struct intel_display *display)
2196 struct i915_power_domains *power_domains = &display->power.domains;
2205 for_each_power_well(display, power_well) {
2210 enabled = intel_power_well_is_enabled(display, power_well);
2214 drm_err(display->drm,
2224 drm_err(display->drm,
2238 intel_power_domains_dump_info(display);
2248 static void intel_power_domains_verify_state(struct intel_display *display)
2254 void intel_display_power_suspend_late(struct intel_display *display, bool s2idle)
2256 intel_power_domains_suspend(display, s2idle);
2258 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
2259 display->platform.broxton) {
2260 bxt_enable_dc9(display);
2261 } else if (display->platform.haswell || display->platform.broadwell) {
2262 hsw_enable_pc8(display);
2266 if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1)
2267 intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2270 void intel_display_power_resume_early(struct intel_display *display)
2272 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake ||
2273 display->platform.broxton) {
2274 gen9_sanitize_dc_state(display);
2275 bxt_disable_dc9(display);
2276 } else if (display->platform.haswell || display->platform.broadwell) {
2277 hsw_disable_pc8(display);
2281 if (INTEL_PCH_TYPE(display) >= PCH_CNP && INTEL_PCH_TYPE(display) < PCH_DG1)
2282 intel_de_rmw(display, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
2284 intel_power_domains_resume(display);
2287 void intel_display_power_suspend(struct intel_display *display)
2289 if (DISPLAY_VER(display) >= 11) {
2290 icl_display_core_uninit(display);
2291 bxt_enable_dc9(display);
2292 } else if (display->platform.geminilake || display->platform.broxton) {
2293 bxt_display_core_uninit(display);
2294 bxt_enable_dc9(display);
2295 } else if (display->platform.haswell || display->platform.broadwell) {
2296 hsw_enable_pc8(display);
2300 void intel_display_power_resume(struct intel_display *display)
2302 struct i915_power_domains *power_domains = &display->power.domains;
2304 if (DISPLAY_VER(display) >= 11) {
2305 bxt_disable_dc9(display);
2306 icl_display_core_init(display, true);
2307 if (intel_dmc_has_payload(display)) {
2309 skl_enable_dc6(display);
2311 gen9_enable_dc5(display);
2313 } else if (display->platform.geminilake || display->platform.broxton) {
2314 bxt_disable_dc9(display);
2315 bxt_display_core_init(display, true);
2316 if (intel_dmc_has_payload(display) &&
2318 gen9_enable_dc5(display);
2319 } else if (display->platform.haswell || display->platform.broadwell) {
2320 hsw_disable_pc8(display);
2324 void intel_display_power_debug(struct intel_display *display, struct seq_file *m)
2326 struct i915_power_domains *power_domains = &display->power.domains;
2474 intel_port_domains_for_platform(struct intel_display *display,
2478 if (DISPLAY_VER(display) >= 13) {
2481 } else if (DISPLAY_VER(display) >= 12) {
2484 } else if (DISPLAY_VER(display) >= 11) {
2494 intel_port_domains_for_port(struct intel_display *display, enum port port)
2500 intel_port_domains_for_platform(display, &domains, &domains_size);
2509 intel_display_power_ddi_io_domain(struct intel_display *display, enum port port)
2511 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
2513 if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID))
2520 intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port)
2522 const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port);
2524 if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID))
2531 intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch)
2537 intel_port_domains_for_platform(display, &domains, &domains_size);
2546 intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch)
2548 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
2550 if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID))
2557 intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch)
2559 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
2561 if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID))
2568 intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch)
2570 const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch);
2572 if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID))