37 bool intel_encoder_is_c10phy(struct intel_encoder *encoder)  in intel_encoder_is_c10phy()  argument
39 	struct intel_display *display = to_intel_display(encoder);  in intel_encoder_is_c10phy()
40 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_encoder_is_c10phy()
66 static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)  in intel_cx0_get_owned_lane_mask()  argument
68 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);  in intel_cx0_get_owned_lane_mask()
90 static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)  in intel_cx0_program_msgbus_timer()  argument
92 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_program_msgbus_timer()
97 			     XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),  in intel_cx0_program_msgbus_timer()
111 static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)  in intel_cx0_phy_transaction_begin()  argument
113 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_phy_transaction_begin()
114 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);  in intel_cx0_phy_transaction_begin()
119 	intel_cx0_program_msgbus_timer(encoder);  in intel_cx0_phy_transaction_begin()
124 static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)  in intel_cx0_phy_transaction_end()  argument
126 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_phy_transaction_end()
127 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);  in intel_cx0_phy_transaction_end()
133 static void intel_clear_response_ready_flag(struct intel_encoder *encoder,  in intel_clear_response_ready_flag()  argument
136 	struct intel_display *display = to_intel_display(encoder);  in intel_clear_response_ready_flag()
139 		     XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),  in intel_clear_response_ready_flag()
143 static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)  in intel_cx0_bus_reset()  argument
145 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_bus_reset()
146 	enum port port = encoder->port;  in intel_cx0_bus_reset()
147 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_cx0_bus_reset()
161 	intel_clear_response_ready_flag(encoder, lane);  in intel_cx0_bus_reset()
164 static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,  in intel_cx0_wait_for_ack()  argument
167 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_wait_for_ack()
168 	enum port port = encoder->port;  in intel_cx0_wait_for_ack()
169 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_cx0_wait_for_ack()
187 		intel_cx0_bus_reset(encoder, lane);  in intel_cx0_wait_for_ack()
196 		intel_cx0_bus_reset(encoder, lane);  in intel_cx0_wait_for_ack()
205 		intel_cx0_bus_reset(encoder, lane);  in intel_cx0_wait_for_ack()
212 static int __intel_cx0_read_once(struct intel_encoder *encoder,  in __intel_cx0_read_once()  argument
215 	struct intel_display *display = to_intel_display(encoder);  in __intel_cx0_read_once()
216 	enum port port = encoder->port;  in __intel_cx0_read_once()
217 	enum phy phy = intel_encoder_to_phy(encoder);  in __intel_cx0_read_once()
226 		intel_cx0_bus_reset(encoder, lane);  in __intel_cx0_read_once()
235 	ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val);  in __intel_cx0_read_once()
239 	intel_clear_response_ready_flag(encoder, lane);  in __intel_cx0_read_once()
247 		intel_cx0_bus_reset(encoder, lane);  in __intel_cx0_read_once()
252 static u8 __intel_cx0_read(struct intel_encoder *encoder,  in __intel_cx0_read()  argument
255 	struct intel_display *display = to_intel_display(encoder);  in __intel_cx0_read()
256 	enum phy phy = intel_encoder_to_phy(encoder);  in __intel_cx0_read()
263 		status = __intel_cx0_read_once(encoder, lane, addr);  in __intel_cx0_read()
276 static u8 intel_cx0_read(struct intel_encoder *encoder,  in intel_cx0_read()  argument
281 	return __intel_cx0_read(encoder, lane, addr);  in intel_cx0_read()
284 static int __intel_cx0_write_once(struct intel_encoder *encoder,  in __intel_cx0_write_once()  argument
287 	struct intel_display *display = to_intel_display(encoder);  in __intel_cx0_write_once()
288 	enum port port = encoder->port;  in __intel_cx0_write_once()
289 	enum phy phy = intel_encoder_to_phy(encoder);  in __intel_cx0_write_once()
298 		intel_cx0_bus_reset(encoder, lane);  in __intel_cx0_write_once()
314 		intel_cx0_bus_reset(encoder, lane);  in __intel_cx0_write_once()
319 		ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);  in __intel_cx0_write_once()
326 		intel_cx0_bus_reset(encoder, lane);  in __intel_cx0_write_once()
330 	intel_clear_response_ready_flag(encoder, lane);  in __intel_cx0_write_once()
338 		intel_cx0_bus_reset(encoder, lane);  in __intel_cx0_write_once()
343 static void __intel_cx0_write(struct intel_encoder *encoder,  in __intel_cx0_write()  argument
346 	struct intel_display *display = to_intel_display(encoder);  in __intel_cx0_write()
347 	enum phy phy = intel_encoder_to_phy(encoder);  in __intel_cx0_write()
354 		status = __intel_cx0_write_once(encoder, lane, addr, data, committed);  in __intel_cx0_write()
364 static void intel_cx0_write(struct intel_encoder *encoder,  in intel_cx0_write()  argument
370 		__intel_cx0_write(encoder, lane, addr, data, committed);  in intel_cx0_write()
373 static void intel_c20_sram_write(struct intel_encoder *encoder,  in intel_c20_sram_write()  argument
376 	struct intel_display *display = to_intel_display(encoder);  in intel_c20_sram_write()
380 	intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);  in intel_c20_sram_write()
381 	intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);  in intel_c20_sram_write()
383 	intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_H, data >> 8, 0);  in intel_c20_sram_write()
384 	intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);  in intel_c20_sram_write()
387 static u16 intel_c20_sram_read(struct intel_encoder *encoder,  in intel_c20_sram_read()  argument
390 	struct intel_display *display = to_intel_display(encoder);  in intel_c20_sram_read()
395 	intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);  in intel_c20_sram_read()
396 	intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);  in intel_c20_sram_read()
398 	val = intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_H);  in intel_c20_sram_read()
400 	val |= intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_L);  in intel_c20_sram_read()
405 static void __intel_cx0_rmw(struct intel_encoder *encoder,  in __intel_cx0_rmw()  argument
410 	old = __intel_cx0_read(encoder, lane, addr);  in __intel_cx0_rmw()
414 		__intel_cx0_write(encoder, lane, addr, val, committed);  in __intel_cx0_rmw()
417 static void intel_cx0_rmw(struct intel_encoder *encoder,  in intel_cx0_rmw()  argument
423 		__intel_cx0_rmw(encoder, lane, addr, clear, set, committed);  in intel_cx0_rmw()
454 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,  in intel_cx0_phy_set_signal_levels()  argument
457 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_phy_set_signal_levels()
462 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);  in intel_cx0_phy_set_signal_levels()
467 	owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);  in intel_cx0_phy_set_signal_levels()
469 	wakeref = intel_cx0_phy_transaction_begin(encoder);  in intel_cx0_phy_set_signal_levels()
471 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);  in intel_cx0_phy_set_signal_levels()
473 		intel_cx0_phy_transaction_end(encoder, wakeref);  in intel_cx0_phy_set_signal_levels()
477 	if (intel_encoder_is_c10phy(encoder)) {  in intel_cx0_phy_set_signal_levels()
478 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),  in intel_cx0_phy_set_signal_levels()
480 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3),  in intel_cx0_phy_set_signal_levels()
484 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_TX(1),  in intel_cx0_phy_set_signal_levels()
491 		int level = intel_ddi_level(encoder, crtc_state, ln);  in intel_cx0_phy_set_signal_levels()
499 		intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0),  in intel_cx0_phy_set_signal_levels()
503 		intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1),  in intel_cx0_phy_set_signal_levels()
507 		intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2),  in intel_cx0_phy_set_signal_levels()
514 	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_OVRD,  in intel_cx0_phy_set_signal_levels()
518 	if (intel_encoder_is_c10phy(encoder))  in intel_cx0_phy_set_signal_levels()
519 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),  in intel_cx0_phy_set_signal_levels()
522 	intel_cx0_phy_transaction_end(encoder, wakeref);  in intel_cx0_phy_set_signal_levels()
2016 			struct intel_encoder *encoder)  in intel_c10pll_tables_get()  argument
2027 	MISSING_CASE(encoder->type);  in intel_c10pll_tables_get()
2031 static void intel_cx0pll_update_ssc(struct intel_encoder *encoder,  in intel_cx0pll_update_ssc()  argument
2034 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0pll_update_ssc()
2038 			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);  in intel_cx0pll_update_ssc()
2045 static void intel_c10pll_update_pll(struct intel_encoder *encoder,  in intel_c10pll_update_pll()  argument
2048 	struct intel_display *display = to_intel_display(encoder);  in intel_c10pll_update_pll()
2059 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,  in intel_c10pll_calc_state_from_table()  argument
2069 			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);  in intel_c10pll_calc_state_from_table()
2070 			intel_c10pll_update_pll(encoder, pll_state);  in intel_c10pll_calc_state_from_table()
2081 				   struct intel_encoder *encoder)  in intel_c10pll_calc_state()  argument
2086 	tables = intel_c10pll_tables_get(crtc_state, encoder);  in intel_c10pll_calc_state()
2090 	err = intel_c10pll_calc_state_from_table(encoder, tables,  in intel_c10pll_calc_state()
2101 	intel_c10pll_update_pll(encoder,  in intel_c10pll_calc_state()
2108 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,  in intel_c10pll_readout_hw_state()  argument
2115 	wakeref = intel_cx0_phy_transaction_begin(encoder);  in intel_c10pll_readout_hw_state()
2121 	intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1),  in intel_c10pll_readout_hw_state()
2126 		pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));  in intel_c10pll_readout_hw_state()
2128 	pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0));  in intel_c10pll_readout_hw_state()
2129 	pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));  in intel_c10pll_readout_hw_state()
2131 	intel_cx0_phy_transaction_end(encoder, wakeref);  in intel_c10pll_readout_hw_state()
2135 				  struct intel_encoder *encoder,  in intel_c10_pll_program()  argument
2140 	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),  in intel_c10_pll_program()
2146 		intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),  in intel_c10_pll_program()
2150 	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);  in intel_c10_pll_program()
2151 	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);  in intel_c10_pll_program()
2154 	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,  in intel_c10_pll_program()
2157 	intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),  in intel_c10_pll_program()
2310 			 struct intel_encoder *encoder)  in intel_c20_pll_tables_get()  argument
2333 	MISSING_CASE(encoder->type);  in intel_c20_pll_tables_get()
2338 				   struct intel_encoder *encoder)  in intel_c20pll_calc_state()  argument
2349 	tables = intel_c20_pll_tables_get(crtc_state, encoder);  in intel_c20pll_calc_state()
2356 			intel_cx0pll_update_ssc(encoder,  in intel_c20pll_calc_state()
2368 			    struct intel_encoder *encoder)  in intel_cx0pll_calc_state()  argument
2370 	if (intel_encoder_is_c10phy(encoder))  in intel_cx0pll_calc_state()
2371 		return intel_c10pll_calc_state(crtc_state, encoder);  in intel_cx0pll_calc_state()
2372 	return intel_c20pll_calc_state(crtc_state, encoder);  in intel_cx0pll_calc_state()
2380 static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,  in intel_c20pll_calc_port_clock()  argument
2425 static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,  in intel_c20pll_readout_hw_state()  argument
2428 	struct intel_display *display = to_intel_display(encoder);  in intel_c20pll_readout_hw_state()
2433 	wakeref = intel_cx0_phy_transaction_begin(encoder);  in intel_c20pll_readout_hw_state()
2436 …cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_…  in intel_c20pll_readout_hw_state()
2441 			pll_state->tx[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2445 			pll_state->tx[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2453 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2457 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2466 				pll_state->mpllb[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2470 				pll_state->mpllb[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2478 				pll_state->mplla[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2482 				pll_state->mplla[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2488 	pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);  in intel_c20pll_readout_hw_state()
2490 	intel_cx0_phy_transaction_end(encoder, wakeref);  in intel_c20pll_readout_hw_state()
2604 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)  in intel_c20_protocol_switch_valid()  argument
2606 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);  in intel_c20_protocol_switch_valid()
2624 				  struct intel_encoder *encoder,  in intel_c20_pll_program()  argument
2628 	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);  in intel_c20_pll_program()
2633 	cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0);  in intel_c20_pll_program()
2640 	if (intel_c20_protocol_switch_valid(encoder)) {  in intel_c20_pll_program()
2642 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);  in intel_c20_pll_program()
2650 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2654 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2662 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2666 			intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2675 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2679 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2686 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2690 				intel_c20_sram_write(encoder, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2697 	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,  in intel_c20_pll_program()
2704 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,  in intel_c20_pll_program()
2709 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,  in intel_c20_pll_program()
2714 		intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,  in intel_c20_pll_program()
2723 	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,  in intel_c20_pll_program()
2727 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,  in intel_c10pll_calc_port_clock()  argument
2754 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,  in intel_program_port_clock_ctl()  argument
2759 	struct intel_display *display = to_intel_display(encoder);  in intel_program_port_clock_ctl()
2762 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),  in intel_program_port_clock_ctl()
2783 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_program_port_clock_ctl()
2811 static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,  in intel_cx0_powerdown_change_sequence()  argument
2814 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_powerdown_change_sequence()
2815 	enum port port = encoder->port;  in intel_cx0_powerdown_change_sequence()
2816 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_cx0_powerdown_change_sequence()
2832 			intel_cx0_bus_reset(encoder, lane);  in intel_cx0_powerdown_change_sequence()
2848 static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)  in intel_cx0_setup_powerdown()  argument
2850 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_setup_powerdown()
2851 	enum port port = encoder->port;  in intel_cx0_setup_powerdown()
2885 static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,  in intel_cx0_phy_lane_reset()  argument
2888 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_phy_lane_reset()
2889 	enum port port = encoder->port;  in intel_cx0_phy_lane_reset()
2890 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_cx0_phy_lane_reset()
2891 	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);  in intel_cx0_phy_lane_reset()
2931 	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,  in intel_cx0_phy_lane_reset()
2933 	intel_cx0_setup_powerdown(encoder);  in intel_cx0_phy_lane_reset()
2945 static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,  in intel_cx0_program_phy_lane()  argument
2950 	bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));  in intel_cx0_program_phy_lane()
2951 	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);  in intel_cx0_program_phy_lane()
2953 	if (intel_encoder_is_c10phy(encoder))  in intel_cx0_program_phy_lane()
2954 		intel_cx0_rmw(encoder, owned_lane_mask,  in intel_cx0_program_phy_lane()
2976 		intel_cx0_rmw(encoder, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),  in intel_cx0_program_phy_lane()
2982 	if (intel_encoder_is_c10phy(encoder))  in intel_cx0_program_phy_lane()
2983 		intel_cx0_rmw(encoder, owned_lane_mask,  in intel_cx0_program_phy_lane()
3011 static void __intel_cx0pll_enable(struct intel_encoder *encoder,  in __intel_cx0pll_enable()  argument
3015 	struct intel_display *display = to_intel_display(encoder);  in __intel_cx0pll_enable()
3016 	enum phy phy = intel_encoder_to_phy(encoder);  in __intel_cx0pll_enable()
3017 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);  in __intel_cx0pll_enable()
3021 	intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);  in __intel_cx0pll_enable()
3027 	intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock, lane_reversal);  in __intel_cx0pll_enable()
3030 	intel_cx0_phy_lane_reset(encoder, lane_reversal);  in __intel_cx0pll_enable()
3036 	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,  in __intel_cx0pll_enable()
3046 	if (intel_encoder_is_c10phy(encoder))  in __intel_cx0pll_enable()
3047 		intel_c10_pll_program(display, encoder, &pll_state->c10);  in __intel_cx0pll_enable()
3049 		intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock);  in __intel_cx0pll_enable()
3055 	intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal);  in __intel_cx0pll_enable()
3066 	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);  in __intel_cx0pll_enable()
3072 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in __intel_cx0pll_enable()
3077 	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in __intel_cx0pll_enable()
3090 	intel_cx0_phy_transaction_end(encoder, wakeref);  in __intel_cx0pll_enable()
3093 static void intel_cx0pll_enable(struct intel_encoder *encoder,  in intel_cx0pll_enable()  argument
3096 	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,  in intel_cx0pll_enable()
3101 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)  in intel_mtl_tbt_calc_port_clock()  argument
3103 	struct intel_display *display = to_intel_display(encoder);  in intel_mtl_tbt_calc_port_clock()
3106 	val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));  in intel_mtl_tbt_calc_port_clock()
3163 static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,  in intel_mtl_tbt_pll_enable()  argument
3166 	struct intel_display *display = to_intel_display(encoder);  in intel_mtl_tbt_pll_enable()
3167 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_mtl_tbt_pll_enable()
3183 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_mtl_tbt_pll_enable()
3187 	val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));  in intel_mtl_tbt_pll_enable()
3198 	intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);  in intel_mtl_tbt_pll_enable()
3201 	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_mtl_tbt_pll_enable()
3206 			 "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",  in intel_mtl_tbt_pll_enable()
3207 			 encoder->base.base.id, encoder->base.name, phy_name(phy));  in intel_mtl_tbt_pll_enable()
3218 	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),  in intel_mtl_tbt_pll_enable()
3222 void intel_mtl_pll_enable(struct intel_encoder *encoder,  in intel_mtl_pll_enable()  argument
3225 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);  in intel_mtl_pll_enable()
3228 		intel_mtl_tbt_pll_enable(encoder, crtc_state);  in intel_mtl_pll_enable()
3230 		intel_cx0pll_enable(encoder, crtc_state);  in intel_mtl_pll_enable()
3238 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,  in intel_lnl_mac_transmit_lfps()  argument
3241 	struct intel_display *display = to_intel_display(encoder);  in intel_lnl_mac_transmit_lfps()
3247 	    !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))  in intel_lnl_mac_transmit_lfps()
3250 	owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);  in intel_lnl_mac_transmit_lfps()
3252 	wakeref = intel_cx0_phy_transaction_begin(encoder);  in intel_lnl_mac_transmit_lfps()
3254 	if (intel_encoder_is_c10phy(encoder))  in intel_lnl_mac_transmit_lfps()
3255 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0,  in intel_lnl_mac_transmit_lfps()
3265 		intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),  in intel_lnl_mac_transmit_lfps()
3270 	intel_cx0_phy_transaction_end(encoder, wakeref);  in intel_lnl_mac_transmit_lfps()
3273 static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)  in cx0_power_control_disable_val()  argument
3275 	struct intel_display *display = to_intel_display(encoder);  in cx0_power_control_disable_val()
3277 	if (intel_encoder_is_c10phy(encoder))  in cx0_power_control_disable_val()
3280 	if ((display->platform.battlemage && encoder->port == PORT_A) ||  in cx0_power_control_disable_val()
3281 	    (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))  in cx0_power_control_disable_val()
3287 static void intel_cx0pll_disable(struct intel_encoder *encoder)  in intel_cx0pll_disable()  argument
3289 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0pll_disable()
3290 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_cx0pll_disable()
3291 	intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);  in intel_cx0pll_disable()
3294 	intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,  in intel_cx0pll_disable()
3295 					    cx0_power_control_disable_val(encoder));  in intel_cx0pll_disable()
3306 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_cx0pll_disable()
3311 	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);  in intel_cx0pll_disable()
3316 	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_cx0pll_disable()
3330 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_cx0pll_disable()
3332 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_cx0pll_disable()
3335 	intel_cx0_phy_transaction_end(encoder, wakeref);  in intel_cx0pll_disable()
3338 static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)  in intel_cx0_pll_is_enabled()  argument
3340 	struct intel_display *display = to_intel_display(encoder);  in intel_cx0_pll_is_enabled()
3341 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);  in intel_cx0_pll_is_enabled()
3344 	return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &  in intel_cx0_pll_is_enabled()
3348 static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)  in intel_mtl_tbt_pll_disable()  argument
3350 	struct intel_display *display = to_intel_display(encoder);  in intel_mtl_tbt_pll_disable()
3351 	enum phy phy = intel_encoder_to_phy(encoder);  in intel_mtl_tbt_pll_disable()
3361 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_mtl_tbt_pll_disable()
3365 	if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_mtl_tbt_pll_disable()
3368 			 "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",  in intel_mtl_tbt_pll_disable()
3369 			 encoder->base.base.id, encoder->base.name, phy_name(phy));  in intel_mtl_tbt_pll_disable()
3379 	intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),  in intel_mtl_tbt_pll_disable()
3384 	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);  in intel_mtl_tbt_pll_disable()
3387 void intel_mtl_pll_disable(struct intel_encoder *encoder)  in intel_mtl_pll_disable()  argument
3389 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);  in intel_mtl_pll_disable()
3392 		intel_mtl_tbt_pll_disable(encoder);  in intel_mtl_pll_disable()
3394 		intel_cx0pll_disable(encoder);  in intel_mtl_pll_disable()
3398 intel_mtl_port_pll_type(struct intel_encoder *encoder,  in intel_mtl_port_pll_type()  argument
3401 	struct intel_display *display = to_intel_display(encoder);  in intel_mtl_port_pll_type()
3408 	val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));  in intel_mtl_port_pll_type()
3420 				      struct intel_encoder *encoder,  in intel_c10pll_state_verify()  argument
3447 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,  in intel_cx0pll_readout_hw_state()  argument
3452 	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));  in intel_cx0pll_readout_hw_state()
3456 	if (intel_encoder_is_c10phy(encoder)) {  in intel_cx0pll_readout_hw_state()
3457 		intel_c10pll_readout_hw_state(encoder, &pll_state->c10);  in intel_cx0pll_readout_hw_state()
3460 		intel_c20pll_readout_hw_state(encoder, &pll_state->c20);  in intel_cx0pll_readout_hw_state()
3516 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,  in intel_cx0pll_calc_port_clock()  argument
3519 	if (intel_encoder_is_c10phy(encoder))  in intel_cx0pll_calc_port_clock()
3520 		return intel_c10pll_calc_port_clock(encoder, &pll_state->c10);  in intel_cx0pll_calc_port_clock()
3522 	return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);  in intel_cx0pll_calc_port_clock()
3527 				      struct intel_encoder *encoder,  in intel_c20pll_state_verify()  argument
3534 	int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);  in intel_c20pll_state_verify()
3584 	struct intel_encoder *encoder;  in intel_cx0pll_state_verify()  local
3598 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);  in intel_cx0pll_state_verify()
3599 	intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);  in intel_cx0pll_state_verify()
3604 	if (intel_encoder_is_c10phy(encoder))  in intel_cx0pll_state_verify()
3605 		intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10);  in intel_cx0pll_state_verify()
3607 		intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20);  in intel_cx0pll_state_verify()
3625 	struct intel_encoder *encoder;  in intel_cx0_pll_power_save_wa()  local
3630 	for_each_intel_encoder(display->drm, encoder) {  in intel_cx0_pll_power_save_wa()
3634 		if (!intel_encoder_is_dig_port(encoder))  in intel_cx0_pll_power_save_wa()
3637 		if (!intel_encoder_is_c10phy(encoder))  in intel_cx0_pll_power_save_wa()
3640 		if (intel_cx0_pll_is_enabled(encoder))  in intel_cx0_pll_power_save_wa()
3643 		if (intel_c10pll_calc_state_from_table(encoder,  in intel_cx0_pll_power_save_wa()
3653 			    "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",  in intel_cx0_pll_power_save_wa()
3654 			    encoder->base.base.id, encoder->base.name);  in intel_cx0_pll_power_save_wa()
3656 		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4);  in intel_cx0_pll_power_save_wa()
3657 		intel_cx0pll_disable(encoder);  in intel_cx0_pll_power_save_wa()