Lines Matching full:encoder
35 bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
37 struct intel_display *display = to_intel_display(encoder);
38 enum phy phy = intel_encoder_to_phy(encoder);
62 static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
64 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
86 static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
88 struct intel_display *display = to_intel_display(encoder);
93 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),
107 static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
109 struct intel_display *display = to_intel_display(encoder);
110 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
115 intel_cx0_program_msgbus_timer(encoder);
120 static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
122 struct intel_display *display = to_intel_display(encoder);
123 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
129 void intel_clear_response_ready_flag(struct intel_encoder *encoder,
132 struct intel_display *display = to_intel_display(encoder);
135 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane),
139 void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
141 struct intel_display *display = to_intel_display(encoder);
142 enum port port = encoder->port;
143 enum phy phy = intel_encoder_to_phy(encoder);
157 intel_clear_response_ready_flag(encoder, lane);
160 int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
163 struct intel_display *display = to_intel_display(encoder);
164 enum port port = encoder->port;
165 enum phy phy = intel_encoder_to_phy(encoder);
181 intel_cx0_bus_reset(encoder, lane);
190 intel_cx0_bus_reset(encoder, lane);
199 intel_cx0_bus_reset(encoder, lane);
206 static int __intel_cx0_read_once(struct intel_encoder *encoder,
209 struct intel_display *display = to_intel_display(encoder);
210 enum port port = encoder->port;
211 enum phy phy = intel_encoder_to_phy(encoder);
220 intel_cx0_bus_reset(encoder, lane);
229 ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val);
233 intel_clear_response_ready_flag(encoder, lane);
241 intel_cx0_bus_reset(encoder, lane);
246 static u8 __intel_cx0_read(struct intel_encoder *encoder,
249 struct intel_display *display = to_intel_display(encoder);
250 enum phy phy = intel_encoder_to_phy(encoder);
257 status = __intel_cx0_read_once(encoder, lane, addr);
270 u8 intel_cx0_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr)
274 return __intel_cx0_read(encoder, lane, addr);
277 static int __intel_cx0_write_once(struct intel_encoder *encoder,
280 struct intel_display *display = to_intel_display(encoder);
281 enum port port = encoder->port;
282 enum phy phy = intel_encoder_to_phy(encoder);
291 intel_cx0_bus_reset(encoder, lane);
307 intel_cx0_bus_reset(encoder, lane);
312 ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
319 intel_cx0_bus_reset(encoder, lane);
323 intel_clear_response_ready_flag(encoder, lane);
331 intel_cx0_bus_reset(encoder, lane);
336 static void __intel_cx0_write(struct intel_encoder *encoder,
339 struct intel_display *display = to_intel_display(encoder);
340 enum phy phy = intel_encoder_to_phy(encoder);
347 status = __intel_cx0_write_once(encoder, lane, addr, data, committed);
357 void intel_cx0_write(struct intel_encoder *encoder,
363 __intel_cx0_write(encoder, lane, addr, data, committed);
366 static void intel_c20_sram_write(struct intel_encoder *encoder,
369 struct intel_display *display = to_intel_display(encoder);
373 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
374 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
376 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
377 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
380 static u16 intel_c20_sram_read(struct intel_encoder *encoder,
383 struct intel_display *display = to_intel_display(encoder);
388 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
389 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
391 val = intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_H);
393 val |= intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_L);
398 static void __intel_cx0_rmw(struct intel_encoder *encoder,
403 old = __intel_cx0_read(encoder, lane, addr);
407 __intel_cx0_write(encoder, lane, addr, val, committed);
410 void intel_cx0_rmw(struct intel_encoder *encoder,
416 __intel_cx0_rmw(encoder, lane, addr, clear, set, committed);
447 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
450 struct intel_display *display = to_intel_display(encoder);
455 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
460 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
462 wakeref = intel_cx0_phy_transaction_begin(encoder);
464 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
466 intel_cx0_phy_transaction_end(encoder, wakeref);
470 if (intel_encoder_is_c10phy(encoder)) {
471 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
473 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3),
477 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_TX(1),
484 int level = intel_ddi_level(encoder, crtc_state, ln);
492 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0),
496 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1),
500 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2),
507 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_OVRD,
511 if (intel_encoder_is_c10phy(encoder))
512 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
515 intel_cx0_phy_transaction_end(encoder, wakeref);
2009 struct intel_encoder *encoder)
2020 MISSING_CASE(encoder->type);
2024 static void intel_cx0pll_update_ssc(struct intel_encoder *encoder,
2027 struct intel_display *display = to_intel_display(encoder);
2031 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2038 static void intel_c10pll_update_pll(struct intel_encoder *encoder,
2041 struct intel_display *display = to_intel_display(encoder);
2052 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
2062 intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
2063 intel_c10pll_update_pll(encoder, pll_state);
2074 struct intel_encoder *encoder)
2079 tables = intel_c10pll_tables_get(crtc_state, encoder);
2083 err = intel_c10pll_calc_state_from_table(encoder, tables,
2094 intel_c10pll_update_pll(encoder,
2101 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
2104 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
2111 wakeref = intel_cx0_phy_transaction_begin(encoder);
2117 intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1),
2122 pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
2124 pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0));
2125 pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0));
2127 intel_cx0_phy_transaction_end(encoder, wakeref);
2129 pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
2133 struct intel_encoder *encoder,
2138 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
2144 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),
2148 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);
2149 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);
2152 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,
2155 intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
2308 struct intel_encoder *encoder)
2331 MISSING_CASE(encoder->type);
2336 struct intel_encoder *encoder)
2347 tables = intel_c20_pll_tables_get(crtc_state, encoder);
2354 intel_cx0pll_update_ssc(encoder,
2366 struct intel_encoder *encoder)
2368 if (intel_encoder_is_c10phy(encoder))
2369 return intel_c10pll_calc_state(crtc_state, encoder);
2370 return intel_c20pll_calc_state(crtc_state, encoder);
2378 static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
2423 static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
2426 struct intel_display *display = to_intel_display(encoder);
2431 wakeref = intel_cx0_phy_transaction_begin(encoder);
2434 cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
2439 pll_state->tx[i] = intel_c20_sram_read(encoder,
2443 pll_state->tx[i] = intel_c20_sram_read(encoder,
2451 pll_state->cmn[i] = intel_c20_sram_read(encoder,
2455 pll_state->cmn[i] = intel_c20_sram_read(encoder,
2464 pll_state->mpllb[i] = intel_c20_sram_read(encoder,
2468 pll_state->mpllb[i] = intel_c20_sram_read(encoder,
2476 pll_state->mplla[i] = intel_c20_sram_read(encoder,
2480 pll_state->mplla[i] = intel_c20_sram_read(encoder,
2486 pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
2488 intel_cx0_phy_transaction_end(encoder, wakeref);
2588 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
2590 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2608 struct intel_encoder *encoder,
2612 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
2618 cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
2626 if (intel_c20_protocol_switch_valid(encoder)) {
2628 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
2636 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2640 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2648 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2652 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2661 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2665 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2672 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2676 intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
2683 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
2696 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
2702 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
2711 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
2716 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
2743 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
2748 struct intel_display *display = to_intel_display(encoder);
2751 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
2772 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
2800 void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
2803 struct intel_display *display = to_intel_display(encoder);
2804 enum port port = encoder->port;
2805 enum phy phy = intel_encoder_to_phy(encoder);
2821 intel_cx0_bus_reset(encoder, lane);
2837 void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
2839 struct intel_display *display = to_intel_display(encoder);
2840 enum port port = encoder->port;
2874 static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
2877 struct intel_display *display = to_intel_display(encoder);
2878 enum port port = encoder->port;
2879 enum phy phy = intel_encoder_to_phy(encoder);
2880 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
2919 intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
2921 intel_cx0_setup_powerdown(encoder);
2933 static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
2938 bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
2939 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
2941 if (intel_encoder_is_c10phy(encoder))
2942 intel_cx0_rmw(encoder, owned_lane_mask,
2964 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
2970 if (intel_encoder_is_c10phy(encoder))
2971 intel_cx0_rmw(encoder, owned_lane_mask,
2999 static void __intel_cx0pll_enable(struct intel_encoder *encoder,
3003 struct intel_display *display = to_intel_display(encoder);
3004 enum phy phy = intel_encoder_to_phy(encoder);
3005 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3009 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
3015 intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock, lane_reversal);
3018 intel_cx0_phy_lane_reset(encoder, lane_reversal);
3024 intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
3034 if (intel_encoder_is_c10phy(encoder))
3035 intel_c10_pll_program(display, encoder, &pll_state->c10);
3037 intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock);
3043 intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal);
3054 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock);
3060 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3065 if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3078 intel_cx0_phy_transaction_end(encoder, wakeref);
3081 static void intel_cx0pll_enable(struct intel_encoder *encoder,
3084 __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
3089 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
3091 struct intel_display *display = to_intel_display(encoder);
3094 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
3151 void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
3154 struct intel_display *display = to_intel_display(encoder);
3155 enum phy phy = intel_encoder_to_phy(encoder);
3171 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3175 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
3186 intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
3189 if (intel_de_wait_for_set_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3191 drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked\n",
3192 encoder->base.base.id, encoder->base.name, phy_name(phy));
3203 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
3207 void intel_mtl_pll_enable(struct intel_encoder *encoder,
3210 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3213 intel_mtl_tbt_pll_enable(encoder, crtc_state);
3215 intel_cx0pll_enable(encoder, crtc_state);
3223 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
3226 struct intel_display *display = to_intel_display(encoder);
3232 !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
3235 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
3237 wakeref = intel_cx0_phy_transaction_begin(encoder);
3239 if (intel_encoder_is_c10phy(encoder))
3240 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0,
3250 intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0),
3255 intel_cx0_phy_transaction_end(encoder, wakeref);
3258 static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
3260 struct intel_display *display = to_intel_display(encoder);
3262 if (intel_encoder_is_c10phy(encoder))
3265 if ((display->platform.battlemage && encoder->port == PORT_A) ||
3266 (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP))
3272 static void intel_cx0pll_disable(struct intel_encoder *encoder)
3274 struct intel_display *display = to_intel_display(encoder);
3275 enum phy phy = intel_encoder_to_phy(encoder);
3276 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
3279 intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
3280 cx0_power_control_disable_val(encoder));
3291 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3296 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
3301 if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3314 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3316 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3319 intel_cx0_phy_transaction_end(encoder, wakeref);
3322 static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
3324 struct intel_display *display = to_intel_display(encoder);
3325 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3328 return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
3332 void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
3334 struct intel_display *display = to_intel_display(encoder);
3335 enum phy phy = intel_encoder_to_phy(encoder);
3345 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3349 if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3351 drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked\n",
3352 encoder->base.base.id, encoder->base.name, phy_name(phy));
3362 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3367 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
3370 void intel_mtl_pll_disable(struct intel_encoder *encoder)
3372 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3375 intel_mtl_tbt_pll_disable(encoder);
3377 intel_cx0pll_disable(encoder);
3381 intel_mtl_port_pll_type(struct intel_encoder *encoder,
3384 struct intel_display *display = to_intel_display(encoder);
3391 val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
3403 struct intel_encoder *encoder,
3430 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
3435 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
3439 if (intel_encoder_is_c10phy(encoder)) {
3440 intel_c10pll_readout_hw_state(encoder, &pll_state->c10);
3443 intel_c20pll_readout_hw_state(encoder, &pll_state->c20);
3499 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
3502 if (intel_encoder_is_c10phy(encoder))
3503 return intel_c10pll_calc_port_clock(encoder, &pll_state->c10);
3505 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);
3510 struct intel_encoder *encoder,
3517 int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
3567 struct intel_encoder *encoder;
3581 encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
3582 intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);
3587 if (intel_encoder_is_c10phy(encoder))
3588 intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10);
3590 intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20);
3608 struct intel_encoder *encoder;
3613 for_each_intel_encoder(display->drm, encoder) {
3617 if (!intel_encoder_is_dig_port(encoder))
3620 if (!intel_encoder_is_c10phy(encoder))
3623 if (intel_cx0_pll_is_enabled(encoder))
3626 if (intel_c10pll_calc_state_from_table(encoder,
3636 "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
3637 encoder->base.base.id, encoder->base.name);
3639 __intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4);
3640 intel_cx0pll_disable(encoder);