535 	.cmn = 0x21,
561 	.cmn = 0x21,
587 	.cmn = 0x21,
613 	.cmn = 0x21,
639 	.cmn = 0x21,
665 	.cmn = 0x21,
691 	.cmn = 0x21,
717 	.cmn = 0x21,
743 	.cmn = 0x21,
794 	.cmn = {0x0500, /* cmn cfg0*/
795 		0x0005, /* cmn cfg1 */
796 		0x0000, /* cmn cfg2 */
797 		0x0000, /* cmn cfg3 */
819 	.cmn = {0x0500, /* cmn cfg0*/
820 		0x0005, /* cmn cfg1 */
821 		0x0000, /* cmn cfg2 */
822 		0x0000, /* cmn cfg3 */
844 	.cmn = {0x0500, /* cmn cfg0*/
845 		0x0005, /* cmn cfg1 */
846 		0x0000, /* cmn cfg2 */
847 		0x0000, /* cmn cfg3 */
869 	.cmn = {0x0500, /* cmn cfg0*/
870 		0x0005, /* cmn cfg1 */
871 		0x0000, /* cmn cfg2 */
872 		0x0000, /* cmn cfg3 */
895 	.cmn = {0x0700, /* cmn cfg0*/
896 		0x0005, /* cmn cfg1 */
897 		0x0000, /* cmn cfg2 */
898 		0x0000, /* cmn cfg3 */
919 	.cmn = {0x0500, /* cmn cfg0*/
920 		0x0005, /* cmn cfg1 */
921 		0x0000, /* cmn cfg2 */
922 		0x0000, /* cmn cfg3 */
944 	.cmn = {0x0500, /* cmn cfg0*/
945 		0x0005, /* cmn cfg1 */
946 		0x0000, /* cmn cfg2 */
947 		0x0000, /* cmn cfg3 */
983 	.cmn = { 0x0500,
1008 	.cmn = { 0x0500,
1033 	.cmn = { 0x0500,
1058 	.cmn = { 0x0500,
1083 	.cmn = { 0x0500,
1121 	.cmn = {0x0500, /* cmn cfg0*/
1122 		0x0005, /* cmn cfg1 */
1123 		0x0000, /* cmn cfg2 */
1124 		0x0000, /* cmn cfg3 */
1173 	.cmn = 0x1,
1199 	.cmn = 0x1,
1225 	.cmn = 0x1,
1251 	.cmn = 0x1,
1277 	.cmn = 0x1,
1304 	.cmn = 0x1,
1314 	.cmn = 0x1,
1324 	.cmn = 0x1,
1334 	.cmn = 0x1,
1344 	.cmn = 0x1,
1354 	.cmn = 0x1,
1364 	.cmn = 0x1,
1374 	.cmn = 0x1,
1384 	.cmn = 0x1,
1394 	.cmn = 0x1,
1404 	.cmn = 0x1,
1414 	.cmn = 0x1,
1424 	.cmn = 0x1,
1434 	.cmn = 0x1,
1444 	.cmn = 0x1,
1454 	.cmn = 0x1,
1464 	.cmn = 0x1,
1474 	.cmn = 0x1,
1484 	.cmn = 0x1,
1494 	.cmn = 0x1,
1504 	.cmn = 0x1,
1514 	.cmn = 0x1,
1524 	.cmn = 0x1,
1534 	.cmn = 0x1,
1544 	.cmn = 0x1,
1554 	.cmn = 0x1,
1564 	.cmn = 0x1,
1574 	.cmn = 0x1,
1584 	.cmn = 0x1,
1594 	.cmn = 0x1,
1604 	.cmn = 0x1,
1614 	.cmn = 0x1,
1624 	.cmn = 0x1,
1634 	.cmn = 0x1,
1644 	.cmn = 0x1,
1654 	.cmn = 0x1,
1664 	.cmn = 0x1,
1674 	.cmn = 0x1,
1684 	.cmn = 0x1,
1694 	.cmn = 0x1,
1756 	.cmn = { 0x0500, /* cmn cfg0*/
1757 		  0x0005, /* cmn cfg1 */
1758 		  0x0000, /* cmn cfg2 */
1759 		  0x0000, /* cmn cfg3 */
1781 	.cmn = { 0x0500, /* cmn cfg0*/
1782 		  0x0005, /* cmn cfg1 */
1783 		  0x0000, /* cmn cfg2 */
1784 		  0x0000, /* cmn cfg3 */
1806 	.cmn = { 0x0500, /* cmn cfg0*/
1807 		  0x0005, /* cmn cfg1 */
1808 		  0x0000, /* cmn cfg2 */
1809 		  0x0000, /* cmn cfg3 */
1831 	.cmn = { 0x0500, /* cmn cfg0*/
1832 		  0x0005, /* cmn cfg1 */
1833 		  0x0000, /* cmn cfg2 */
1834 		  0x0000, /* cmn cfg3 */
1856 	.cmn = { 0x0500, /* cmn cfg0*/
1857 		  0x0005, /* cmn cfg1 */
1858 		  0x0000, /* cmn cfg2 */
1859 		  0x0000, /* cmn cfg3 */
1881 	.cmn = { 0x0500, /* cmn cfg0*/
1882 		  0x0005, /* cmn cfg1 */
1883 		  0x0000, /* cmn cfg2 */
1884 		  0x0000, /* cmn cfg3 */
1906 	.cmn = { 0x0500, /* cmn cfg0*/
1907 		  0x0005, /* cmn cfg1 */
1908 		  0x0000, /* cmn cfg2 */
1909 		  0x0000, /* cmn cfg3 */
1931 	.cmn = { 0x0500, /* cmn cfg0*/
1932 		  0x0005, /* cmn cfg1 */
1933 		  0x0000, /* cmn cfg2 */
1934 		  0x0000, /* cmn cfg3 */
1956 	.cmn = { 0x0500, /* cmn cfg0*/
1957 		  0x0005, /* cmn cfg1 */
1958 		  0x0000, /* cmn cfg2 */
1959 		  0x0000, /* cmn cfg3 */
1981 	.cmn = { 0x0500, /* cmn cfg0*/
1982 		  0x0005, /* cmn cfg1 */
1983 		  0x0000, /* cmn cfg2 */
1984 		  0x0000, /* cmn cfg3 */
2128 	pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0));  in intel_c10pll_readout_hw_state()
2150 	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);  in intel_c10_pll_program()
2189 	drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,  in intel_c10pll_dump_hw_state()
2190 		    hw_state->cmn);  in intel_c10pll_dump_hw_state()
2282 	pll_state->cmn[0]	= 0x0500;  in intel_c20_compute_hdmi_tmds_pll()
2283 	pll_state->cmn[1]	= 0x0005;  in intel_c20_compute_hdmi_tmds_pll()
2284 	pll_state->cmn[2]	= 0x0000;  in intel_c20_compute_hdmi_tmds_pll()
2285 	pll_state->cmn[3]	= 0x0000;  in intel_c20_compute_hdmi_tmds_pll()
2451 	for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {  in intel_c20pll_readout_hw_state()
2453 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2457 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2503 		    "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",  in intel_c20pll_dump_hw_state()
2504 		    hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);  in intel_c20pll_dump_hw_state()
2660 	for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {  in intel_c20_pll_program()
2664 					     pll_state->cmn[i]);  in intel_c20_pll_program()
2668 					     pll_state->cmn[i]);  in intel_c20_pll_program()
3441 	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn,  in intel_c10pll_state_verify()
3444 				 mpllb_sw_state->cmn, mpllb_hw_state->cmn);  in intel_c10pll_state_verify()
3470 	if (a->cmn != b->cmn)  in mtl_compare_hw_state_c10()
3485 	if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0)  in mtl_compare_hw_state_c20()
3570 	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {  in intel_c20pll_state_verify()
3571 		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],  in intel_c20pll_state_verify()
3572 					 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",  in intel_c20pll_state_verify()
3574 					 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);  in intel_c20pll_state_verify()