Lines Matching +full:0 +full:x84
30 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
33 #define INTEL_CX0_LANE0 BIT(0)
61 return 0; in lane_mask_to_lane()
74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
140 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); in intel_clear_response_ready_flag()
178 "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
193 "PHY %c Error occurred during %s command. Status: 0x%x\n", in intel_cx0_wait_for_ack()
202 "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", in intel_cx0_wait_for_ack()
209 return 0; in intel_cx0_wait_for_ack()
236 if (ack < 0) in __intel_cx0_read_once()
262 for (i = 0; i < 3; i++) { in __intel_cx0_read()
265 if (status >= 0) in __intel_cx0_read()
273 return 0; in __intel_cx0_read()
320 if (ack < 0) in __intel_cx0_write_once()
340 return 0; in __intel_cx0_write_once()
353 for (i = 0; i < 3; i++) { in __intel_cx0_write()
356 if (status == 0) in __intel_cx0_write()
380 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_write()
381 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); in intel_c20_sram_write()
383 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_H, data >> 8, 0); in intel_c20_sram_write()
384 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
395 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_read()
396 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
479 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
490 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
494 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_phy_set_signal_levels()
499 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), in intel_cx0_phy_set_signal_levels()
513 /* Write Override enables in 0xD71 */ in intel_cx0_phy_set_signal_levels()
515 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, in intel_cx0_phy_set_signal_levels()
520 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
528 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
529 * programmed 0.
534 .tx = 0x10,
535 .cmn = 0x21,
536 .pll[0] = 0xB4,
537 .pll[1] = 0,
538 .pll[2] = 0x30,
539 .pll[3] = 0x1,
540 .pll[4] = 0x26,
541 .pll[5] = 0x0C,
542 .pll[6] = 0x98,
543 .pll[7] = 0x46,
544 .pll[8] = 0x1,
545 .pll[9] = 0x1,
546 .pll[10] = 0,
547 .pll[11] = 0,
548 .pll[12] = 0xC0,
549 .pll[13] = 0,
550 .pll[14] = 0,
551 .pll[15] = 0x2,
552 .pll[16] = 0x84,
553 .pll[17] = 0x4F,
554 .pll[18] = 0xE5,
555 .pll[19] = 0x23,
560 .tx = 0x10,
561 .cmn = 0x21,
562 .pll[0] = 0x4,
563 .pll[1] = 0,
564 .pll[2] = 0xA2,
565 .pll[3] = 0x1,
566 .pll[4] = 0x33,
567 .pll[5] = 0x10,
568 .pll[6] = 0x75,
569 .pll[7] = 0xB3,
570 .pll[8] = 0x1,
571 .pll[9] = 0x1,
572 .pll[10] = 0,
573 .pll[11] = 0,
574 .pll[12] = 0,
575 .pll[13] = 0,
576 .pll[14] = 0,
577 .pll[15] = 0x2,
578 .pll[16] = 0x85,
579 .pll[17] = 0x0F,
580 .pll[18] = 0xE6,
581 .pll[19] = 0x23,
586 .tx = 0x10,
587 .cmn = 0x21,
588 .pll[0] = 0x34,
589 .pll[1] = 0,
590 .pll[2] = 0xDA,
591 .pll[3] = 0x1,
592 .pll[4] = 0x39,
593 .pll[5] = 0x12,
594 .pll[6] = 0xE3,
595 .pll[7] = 0xE9,
596 .pll[8] = 0x1,
597 .pll[9] = 0x1,
598 .pll[10] = 0,
599 .pll[11] = 0,
600 .pll[12] = 0x20,
601 .pll[13] = 0,
602 .pll[14] = 0,
603 .pll[15] = 0x2,
604 .pll[16] = 0x85,
605 .pll[17] = 0x8F,
606 .pll[18] = 0xE6,
607 .pll[19] = 0x23,
612 .tx = 0x10,
613 .cmn = 0x21,
614 .pll[0] = 0xF4,
615 .pll[1] = 0,
616 .pll[2] = 0xF8,
617 .pll[3] = 0x0,
618 .pll[4] = 0x20,
619 .pll[5] = 0x0A,
620 .pll[6] = 0x29,
621 .pll[7] = 0x10,
622 .pll[8] = 0x1, /* Verify */
623 .pll[9] = 0x1,
624 .pll[10] = 0,
625 .pll[11] = 0,
626 .pll[12] = 0xA0,
627 .pll[13] = 0,
628 .pll[14] = 0,
629 .pll[15] = 0x1,
630 .pll[16] = 0x84,
631 .pll[17] = 0x4F,
632 .pll[18] = 0xE5,
633 .pll[19] = 0x23,
638 .tx = 0x10,
639 .cmn = 0x21,
640 .pll[0] = 0xB4,
641 .pll[1] = 0,
642 .pll[2] = 0x30,
643 .pll[3] = 0x1,
644 .pll[4] = 0x26,
645 .pll[5] = 0x0C,
646 .pll[6] = 0x98,
647 .pll[7] = 0x46,
648 .pll[8] = 0x1,
649 .pll[9] = 0x1,
650 .pll[10] = 0,
651 .pll[11] = 0,
652 .pll[12] = 0xC0,
653 .pll[13] = 0,
654 .pll[14] = 0,
655 .pll[15] = 0x1,
656 .pll[16] = 0x85,
657 .pll[17] = 0x4F,
658 .pll[18] = 0xE6,
659 .pll[19] = 0x23,
664 .tx = 0x10,
665 .cmn = 0x21,
666 .pll[0] = 0x4,
667 .pll[1] = 0,
668 .pll[2] = 0xA2,
669 .pll[3] = 0x1,
670 .pll[4] = 0x33,
671 .pll[5] = 0x10,
672 .pll[6] = 0x75,
673 .pll[7] = 0xB3,
674 .pll[8] = 0x1,
675 .pll[9] = 0x1,
676 .pll[10] = 0,
677 .pll[11] = 0,
678 .pll[12] = 0,
679 .pll[13] = 0,
680 .pll[14] = 0,
681 .pll[15] = 0x1,
682 .pll[16] = 0x85,
683 .pll[17] = 0x0F,
684 .pll[18] = 0xE6,
685 .pll[19] = 0x23,
690 .tx = 0x10,
691 .cmn = 0x21,
692 .pll[0] = 0xF4,
693 .pll[1] = 0,
694 .pll[2] = 0xF8,
695 .pll[3] = 0,
696 .pll[4] = 0x20,
697 .pll[5] = 0x0A,
698 .pll[6] = 0x29,
699 .pll[7] = 0x10,
700 .pll[8] = 0x1,
701 .pll[9] = 0x1,
702 .pll[10] = 0,
703 .pll[11] = 0,
704 .pll[12] = 0xA0,
705 .pll[13] = 0,
706 .pll[14] = 0,
707 .pll[15] = 0,
708 .pll[16] = 0x84,
709 .pll[17] = 0x4F,
710 .pll[18] = 0xE5,
711 .pll[19] = 0x23,
716 .tx = 0x10,
717 .cmn = 0x21,
718 .pll[0] = 0xB4,
719 .pll[1] = 0,
720 .pll[2] = 0x3E,
721 .pll[3] = 0x1,
722 .pll[4] = 0xA8,
723 .pll[5] = 0x0C,
724 .pll[6] = 0x33,
725 .pll[7] = 0x54,
726 .pll[8] = 0x1,
727 .pll[9] = 0x1,
728 .pll[10] = 0,
729 .pll[11] = 0,
730 .pll[12] = 0xC8,
731 .pll[13] = 0,
732 .pll[14] = 0,
733 .pll[15] = 0,
734 .pll[16] = 0x85,
735 .pll[17] = 0x8F,
736 .pll[18] = 0xE6,
737 .pll[19] = 0x23,
742 .tx = 0x10,
743 .cmn = 0x21,
744 .pll[0] = 0x34,
745 .pll[1] = 0,
746 .pll[2] = 0x84,
747 .pll[3] = 0x1,
748 .pll[4] = 0x30,
749 .pll[5] = 0x0F,
750 .pll[6] = 0x3D,
751 .pll[7] = 0x98,
752 .pll[8] = 0x1,
753 .pll[9] = 0x1,
754 .pll[10] = 0,
755 .pll[11] = 0,
756 .pll[12] = 0xF0,
757 .pll[13] = 0,
758 .pll[14] = 0,
759 .pll[15] = 0,
760 .pll[16] = 0x84,
761 .pll[17] = 0x0F,
762 .pll[18] = 0xE5,
763 .pll[19] = 0x23,
790 .tx = { 0xbe88, /* tx cfg0 */
791 0x5800, /* tx cfg1 */
792 0x0000, /* tx cfg2 */
794 .cmn = {0x0500, /* cmn cfg0*/
795 0x0005, /* cmn cfg1 */
796 0x0000, /* cmn cfg2 */
797 0x0000, /* cmn cfg3 */
799 .mpllb = { 0x50a8, /* mpllb cfg0 */
800 0x2120, /* mpllb cfg1 */
801 0xcd9a, /* mpllb cfg2 */
802 0xbfc1, /* mpllb cfg3 */
803 0x5ab8, /* mpllb cfg4 */
804 0x4c34, /* mpllb cfg5 */
805 0x2000, /* mpllb cfg6 */
806 0x0001, /* mpllb cfg7 */
807 0x6000, /* mpllb cfg8 */
808 0x0000, /* mpllb cfg9 */
809 0x0000, /* mpllb cfg10 */
815 .tx = { 0xbe88, /* tx cfg0 */
816 0x4800, /* tx cfg1 */
817 0x0000, /* tx cfg2 */
819 .cmn = {0x0500, /* cmn cfg0*/
820 0x0005, /* cmn cfg1 */
821 0x0000, /* cmn cfg2 */
822 0x0000, /* cmn cfg3 */
824 .mpllb = { 0x308c, /* mpllb cfg0 */
825 0x2110, /* mpllb cfg1 */
826 0xcc9c, /* mpllb cfg2 */
827 0xbfc1, /* mpllb cfg3 */
828 0x4b9a, /* mpllb cfg4 */
829 0x3f81, /* mpllb cfg5 */
830 0x2000, /* mpllb cfg6 */
831 0x0001, /* mpllb cfg7 */
832 0x5000, /* mpllb cfg8 */
833 0x0000, /* mpllb cfg9 */
834 0x0000, /* mpllb cfg10 */
840 .tx = { 0xbe88, /* tx cfg0 */
841 0x4800, /* tx cfg1 */
842 0x0000, /* tx cfg2 */
844 .cmn = {0x0500, /* cmn cfg0*/
845 0x0005, /* cmn cfg1 */
846 0x0000, /* cmn cfg2 */
847 0x0000, /* cmn cfg3 */
849 .mpllb = { 0x108c, /* mpllb cfg0 */
850 0x2108, /* mpllb cfg1 */
851 0xcc9c, /* mpllb cfg2 */
852 0xbfc1, /* mpllb cfg3 */
853 0x4b9a, /* mpllb cfg4 */
854 0x3f81, /* mpllb cfg5 */
855 0x2000, /* mpllb cfg6 */
856 0x0001, /* mpllb cfg7 */
857 0x5000, /* mpllb cfg8 */
858 0x0000, /* mpllb cfg9 */
859 0x0000, /* mpllb cfg10 */
865 .tx = { 0xbe88, /* tx cfg0 */
866 0x4800, /* tx cfg1 */
867 0x0000, /* tx cfg2 */
869 .cmn = {0x0500, /* cmn cfg0*/
870 0x0005, /* cmn cfg1 */
871 0x0000, /* cmn cfg2 */
872 0x0000, /* cmn cfg3 */
874 .mpllb = { 0x10d2, /* mpllb cfg0 */
875 0x2108, /* mpllb cfg1 */
876 0x8d98, /* mpllb cfg2 */
877 0xbfc1, /* mpllb cfg3 */
878 0x7166, /* mpllb cfg4 */
879 0x5f42, /* mpllb cfg5 */
880 0x2000, /* mpllb cfg6 */
881 0x0001, /* mpllb cfg7 */
882 0x7800, /* mpllb cfg8 */
883 0x0000, /* mpllb cfg9 */
884 0x0000, /* mpllb cfg10 */
891 .tx = { 0xbe21, /* tx cfg0 */
892 0xe800, /* tx cfg1 */
893 0x0000, /* tx cfg2 */
895 .cmn = {0x0700, /* cmn cfg0*/
896 0x0005, /* cmn cfg1 */
897 0x0000, /* cmn cfg2 */
898 0x0000, /* cmn cfg3 */
900 .mplla = { 0x3104, /* mplla cfg0 */
901 0xd105, /* mplla cfg1 */
902 0xc025, /* mplla cfg2 */
903 0xc025, /* mplla cfg3 */
904 0x8c00, /* mplla cfg4 */
905 0x759a, /* mplla cfg5 */
906 0x4000, /* mplla cfg6 */
907 0x0003, /* mplla cfg7 */
908 0x3555, /* mplla cfg8 */
909 0x0001, /* mplla cfg9 */
915 .tx = { 0xbea0, /* tx cfg0 */
916 0x4800, /* tx cfg1 */
917 0x0000, /* tx cfg2 */
919 .cmn = {0x0500, /* cmn cfg0*/
920 0x0005, /* cmn cfg1 */
921 0x0000, /* cmn cfg2 */
922 0x0000, /* cmn cfg3 */
924 .mpllb = { 0x015f, /* mpllb cfg0 */
925 0x2205, /* mpllb cfg1 */
926 0x1b17, /* mpllb cfg2 */
927 0xffc1, /* mpllb cfg3 */
928 0xe100, /* mpllb cfg4 */
929 0xbd00, /* mpllb cfg5 */
930 0x2000, /* mpllb cfg6 */
931 0x0001, /* mpllb cfg7 */
932 0x4800, /* mpllb cfg8 */
933 0x0000, /* mpllb cfg9 */
934 0x0000, /* mpllb cfg10 */
940 .tx = { 0xbe20, /* tx cfg0 */
941 0x4800, /* tx cfg1 */
942 0x0000, /* tx cfg2 */
944 .cmn = {0x0500, /* cmn cfg0*/
945 0x0005, /* cmn cfg1 */
946 0x0000, /* cmn cfg2 */
947 0x0000, /* cmn cfg3 */
949 .mplla = { 0x3104, /* mplla cfg0 */
950 0xd105, /* mplla cfg1 */
951 0x9217, /* mplla cfg2 */
952 0x9217, /* mplla cfg3 */
953 0x8c00, /* mplla cfg4 */
954 0x759a, /* mplla cfg5 */
955 0x4000, /* mplla cfg6 */
956 0x0003, /* mplla cfg7 */
957 0x3555, /* mplla cfg8 */
958 0x0001, /* mplla cfg9 */
979 .tx = { 0xbe88,
980 0x4800,
981 0x0000,
983 .cmn = { 0x0500,
984 0x0005,
985 0x0000,
986 0x0000,
988 .mpllb = { 0x50e1,
989 0x2120,
990 0x8e18,
991 0xbfc1,
992 0x9000,
993 0x78f6,
994 0x0000,
995 0x0000,
996 0x0000,
997 0x0000,
998 0x0000,
1004 .tx = { 0xbe88,
1005 0x4800,
1006 0x0000,
1008 .cmn = { 0x0500,
1009 0x0005,
1010 0x0000,
1011 0x0000,
1013 .mpllb = { 0x50fd,
1014 0x2120,
1015 0x8f18,
1016 0xbfc1,
1017 0xa200,
1018 0x8814,
1019 0x2000,
1020 0x0001,
1021 0x1000,
1022 0x0000,
1023 0x0000,
1029 .tx = { 0xbe88,
1030 0x4800,
1031 0x0000,
1033 .cmn = { 0x0500,
1034 0x0005,
1035 0x0000,
1036 0x0000,
1038 .mpllb = { 0x30a8,
1039 0x2110,
1040 0xcd9a,
1041 0xbfc1,
1042 0x6c00,
1043 0x5ab8,
1044 0x2000,
1045 0x0001,
1046 0x6000,
1047 0x0000,
1048 0x0000,
1054 .tx = { 0xbe88,
1055 0x4800,
1056 0x0000,
1058 .cmn = { 0x0500,
1059 0x0005,
1060 0x0000,
1061 0x0000,
1063 .mpllb = { 0x30e1,
1064 0x2110,
1065 0x8e18,
1066 0xbfc1,
1067 0x9000,
1068 0x78f6,
1069 0x0000,
1070 0x0000,
1071 0x0000,
1072 0x0000,
1073 0x0000,
1079 .tx = { 0xbe88,
1080 0x4800,
1081 0x0000,
1083 .cmn = { 0x0500,
1084 0x0005,
1085 0x0000,
1086 0x0000,
1088 .mpllb = { 0x10af,
1089 0x2108,
1090 0xce1a,
1091 0xbfc1,
1092 0x7080,
1093 0x5e80,
1094 0x2000,
1095 0x0001,
1096 0x6400,
1097 0x0000,
1098 0x0000,
1117 .tx = { 0xbea0, /* tx cfg0 */
1118 0x4800, /* tx cfg1 */
1119 0x0000, /* tx cfg2 */
1121 .cmn = {0x0500, /* cmn cfg0*/
1122 0x0005, /* cmn cfg1 */
1123 0x0000, /* cmn cfg2 */
1124 0x0000, /* cmn cfg3 */
1126 .mpllb = { 0x015f, /* mpllb cfg0 */
1127 0x2205, /* mpllb cfg1 */
1128 0x1b17, /* mpllb cfg2 */
1129 0xffc1, /* mpllb cfg3 */
1130 0xbd00, /* mpllb cfg4 */
1131 0x9ec3, /* mpllb cfg5 */
1132 0x2000, /* mpllb cfg6 */
1133 0x0001, /* mpllb cfg7 */
1134 0x4800, /* mpllb cfg8 */
1135 0x0000, /* mpllb cfg9 */
1136 0x0000, /* mpllb cfg10 */
1172 .tx = 0x10,
1173 .cmn = 0x1,
1174 .pll[0] = 0x4,
1175 .pll[1] = 0,
1176 .pll[2] = 0xB2,
1177 .pll[3] = 0,
1178 .pll[4] = 0,
1179 .pll[5] = 0,
1180 .pll[6] = 0,
1181 .pll[7] = 0,
1182 .pll[8] = 0x20,
1183 .pll[9] = 0x1,
1184 .pll[10] = 0,
1185 .pll[11] = 0,
1186 .pll[12] = 0,
1187 .pll[13] = 0,
1188 .pll[14] = 0,
1189 .pll[15] = 0xD,
1190 .pll[16] = 0x6,
1191 .pll[17] = 0x8F,
1192 .pll[18] = 0x84,
1193 .pll[19] = 0x23,
1198 .tx = 0x10,
1199 .cmn = 0x1,
1200 .pll[0] = 0x34,
1201 .pll[1] = 0,
1202 .pll[2] = 0xC0,
1203 .pll[3] = 0,
1204 .pll[4] = 0,
1205 .pll[5] = 0,
1206 .pll[6] = 0,
1207 .pll[7] = 0,
1208 .pll[8] = 0x20,
1209 .pll[9] = 0x1,
1210 .pll[10] = 0,
1211 .pll[11] = 0,
1212 .pll[12] = 0x80,
1213 .pll[13] = 0,
1214 .pll[14] = 0,
1215 .pll[15] = 0xD,
1216 .pll[16] = 0x6,
1217 .pll[17] = 0xCF,
1218 .pll[18] = 0x84,
1219 .pll[19] = 0x23,
1224 .tx = 0x10,
1225 .cmn = 0x1,
1226 .pll[0] = 0xF4,
1227 .pll[1] = 0,
1228 .pll[2] = 0x7A,
1229 .pll[3] = 0,
1230 .pll[4] = 0,
1231 .pll[5] = 0,
1232 .pll[6] = 0,
1233 .pll[7] = 0,
1234 .pll[8] = 0x20,
1235 .pll[9] = 0x1,
1236 .pll[10] = 0,
1237 .pll[11] = 0,
1238 .pll[12] = 0x58,
1239 .pll[13] = 0,
1240 .pll[14] = 0,
1241 .pll[15] = 0xB,
1242 .pll[16] = 0x6,
1243 .pll[17] = 0xF,
1244 .pll[18] = 0x85,
1245 .pll[19] = 0x23,
1250 .tx = 0x10,
1251 .cmn = 0x1,
1252 .pll[0] = 0xF4,
1253 .pll[1] = 0,
1254 .pll[2] = 0x7A,
1255 .pll[3] = 0,
1256 .pll[4] = 0,
1257 .pll[5] = 0,
1258 .pll[6] = 0,
1259 .pll[7] = 0,
1260 .pll[8] = 0x20,
1261 .pll[9] = 0x1,
1262 .pll[10] = 0,
1263 .pll[11] = 0,
1264 .pll[12] = 0x58,
1265 .pll[13] = 0,
1266 .pll[14] = 0,
1267 .pll[15] = 0xA,
1268 .pll[16] = 0x6,
1269 .pll[17] = 0xF,
1270 .pll[18] = 0x85,
1271 .pll[19] = 0x23,
1276 .tx = 0x10,
1277 .cmn = 0x1,
1278 .pll[0] = 0xF4,
1279 .pll[1] = 0,
1280 .pll[2] = 0x7A,
1281 .pll[3] = 0,
1282 .pll[4] = 0,
1283 .pll[5] = 0,
1284 .pll[6] = 0,
1285 .pll[7] = 0,
1286 .pll[8] = 0x20,
1287 .pll[9] = 0x1,
1288 .pll[10] = 0,
1289 .pll[11] = 0,
1290 .pll[12] = 0x58,
1291 .pll[13] = 0,
1292 .pll[14] = 0,
1293 .pll[15] = 0x8,
1294 .pll[16] = 0x6,
1295 .pll[17] = 0xF,
1296 .pll[18] = 0x85,
1297 .pll[19] = 0x23,
1303 .tx = 0x10,
1304 .cmn = 0x1,
1305 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1306 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1307 .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC,
1308 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1313 .tx = 0x10,
1314 .cmn = 0x1,
1315 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1316 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1317 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1318 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1323 .tx = 0x10,
1324 .cmn = 0x1,
1325 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1326 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1327 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1328 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1333 .tx = 0x10,
1334 .cmn = 0x1,
1335 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1336 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1337 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00,
1338 .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1343 .tx = 0x10,
1344 .cmn = 0x1,
1345 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1346 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1347 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1348 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1353 .tx = 0x10,
1354 .cmn = 0x1,
1355 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1356 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1357 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55,
1358 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1363 .tx = 0x10,
1364 .cmn = 0x1,
1365 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1366 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1367 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1368 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1373 .tx = 0x10,
1374 .cmn = 0x1,
1375 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1376 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1377 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA,
1378 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1383 .tx = 0x10,
1384 .cmn = 0x1,
1385 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1386 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1387 .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77,
1388 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1393 .tx = 0x10,
1394 .cmn = 0x1,
1395 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1396 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1397 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55,
1398 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1403 .tx = 0x10,
1404 .cmn = 0x1,
1405 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1406 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1407 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55,
1408 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1413 .tx = 0x10,
1414 .cmn = 0x1,
1415 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1416 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1417 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1418 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1423 .tx = 0x10,
1424 .cmn = 0x1,
1425 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1426 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1427 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1428 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1433 .tx = 0x10,
1434 .cmn = 0x1,
1435 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1436 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1437 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1438 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1443 .tx = 0x10,
1444 .cmn = 0x1,
1445 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1446 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1447 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00,
1448 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1453 .tx = 0x10,
1454 .cmn = 0x1,
1455 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1456 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1457 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00,
1458 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1463 .tx = 0x10,
1464 .cmn = 0x1,
1465 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1466 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1467 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA,
1468 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1473 .tx = 0x10,
1474 .cmn = 0x1,
1475 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1476 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1477 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00,
1478 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1483 .tx = 0x10,
1484 .cmn = 0x1,
1485 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1486 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1487 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00,
1488 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1493 .tx = 0x10,
1494 .cmn = 0x1,
1495 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1496 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1497 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1498 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1503 .tx = 0x10,
1504 .cmn = 0x1,
1505 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1506 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1507 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1508 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1513 .tx = 0x10,
1514 .cmn = 0x1,
1515 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1516 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1517 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1518 .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1523 .tx = 0x10,
1524 .cmn = 0x1,
1525 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1526 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1527 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA,
1528 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1533 .tx = 0x10,
1534 .cmn = 0x1,
1535 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1536 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1537 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55,
1538 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1543 .tx = 0x10,
1544 .cmn = 0x1,
1545 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1546 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1547 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1548 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1553 .tx = 0x10,
1554 .cmn = 0x1,
1555 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1556 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1557 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55,
1558 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1563 .tx = 0x10,
1564 .cmn = 0x1,
1565 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1566 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1567 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00,
1568 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1573 .tx = 0x10,
1574 .cmn = 0x1,
1575 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1576 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1577 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA,
1578 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1583 .tx = 0x10,
1584 .cmn = 0x1,
1585 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1586 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1587 .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99,
1588 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1593 .tx = 0x10,
1594 .cmn = 0x1,
1595 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1596 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1597 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1598 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1603 .tx = 0x10,
1604 .cmn = 0x1,
1605 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1606 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1607 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55,
1608 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1613 .tx = 0x10,
1614 .cmn = 0x1,
1615 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1616 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1617 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00,
1618 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1623 .tx = 0x10,
1624 .cmn = 0x1,
1625 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1626 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1627 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA,
1628 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1633 .tx = 0x10,
1634 .cmn = 0x1,
1635 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1636 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1637 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00,
1638 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1643 .tx = 0x10,
1644 .cmn = 0x1,
1645 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1646 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1647 .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33,
1648 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1653 .tx = 0x10,
1654 .cmn = 0x1,
1655 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1656 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1657 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00,
1658 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1663 .tx = 0x10,
1664 .cmn = 0x1,
1665 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1666 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1667 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA,
1668 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1673 .tx = 0x10,
1674 .cmn = 0x1,
1675 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1676 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1677 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55,
1678 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1683 .tx = 0x10,
1684 .cmn = 0x1,
1685 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1686 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1687 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55,
1688 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1693 .tx = 0x10,
1694 .cmn = 0x1,
1695 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1696 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1697 .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB,
1698 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1752 .tx = { 0xbe88, /* tx cfg0 */
1753 0x9800, /* tx cfg1 */
1754 0x0000, /* tx cfg2 */
1756 .cmn = { 0x0500, /* cmn cfg0*/
1757 0x0005, /* cmn cfg1 */
1758 0x0000, /* cmn cfg2 */
1759 0x0000, /* cmn cfg3 */
1761 .mpllb = { 0xa0d2, /* mpllb cfg0 */
1762 0x7d80, /* mpllb cfg1 */
1763 0x0906, /* mpllb cfg2 */
1764 0xbe40, /* mpllb cfg3 */
1765 0x0000, /* mpllb cfg4 */
1766 0x0000, /* mpllb cfg5 */
1767 0x0200, /* mpllb cfg6 */
1768 0x0001, /* mpllb cfg7 */
1769 0x0000, /* mpllb cfg8 */
1770 0x0000, /* mpllb cfg9 */
1771 0x0001, /* mpllb cfg10 */
1777 .tx = { 0xbe88, /* tx cfg0 */
1778 0x9800, /* tx cfg1 */
1779 0x0000, /* tx cfg2 */
1781 .cmn = { 0x0500, /* cmn cfg0*/
1782 0x0005, /* cmn cfg1 */
1783 0x0000, /* cmn cfg2 */
1784 0x0000, /* cmn cfg3 */
1786 .mpllb = { 0xa0e0, /* mpllb cfg0 */
1787 0x7d80, /* mpllb cfg1 */
1788 0x0906, /* mpllb cfg2 */
1789 0xbe40, /* mpllb cfg3 */
1790 0x0000, /* mpllb cfg4 */
1791 0x0000, /* mpllb cfg5 */
1792 0x2200, /* mpllb cfg6 */
1793 0x0001, /* mpllb cfg7 */
1794 0x8000, /* mpllb cfg8 */
1795 0x0000, /* mpllb cfg9 */
1796 0x0001, /* mpllb cfg10 */
1802 .tx = { 0xbe88, /* tx cfg0 */
1803 0x9800, /* tx cfg1 */
1804 0x0000, /* tx cfg2 */
1806 .cmn = { 0x0500, /* cmn cfg0*/
1807 0x0005, /* cmn cfg1 */
1808 0x0000, /* cmn cfg2 */
1809 0x0000, /* cmn cfg3 */
1811 .mpllb = { 0x609a, /* mpllb cfg0 */
1812 0x7d40, /* mpllb cfg1 */
1813 0xca06, /* mpllb cfg2 */
1814 0xbe40, /* mpllb cfg3 */
1815 0x0000, /* mpllb cfg4 */
1816 0x0000, /* mpllb cfg5 */
1817 0x2200, /* mpllb cfg6 */
1818 0x0001, /* mpllb cfg7 */
1819 0x5800, /* mpllb cfg8 */
1820 0x0000, /* mpllb cfg9 */
1821 0x0001, /* mpllb cfg10 */
1827 .tx = { 0xbe88, /* tx cfg0 */
1828 0x9800, /* tx cfg1 */
1829 0x0000, /* tx cfg2 */
1831 .cmn = { 0x0500, /* cmn cfg0*/
1832 0x0005, /* cmn cfg1 */
1833 0x0000, /* cmn cfg2 */
1834 0x0000, /* cmn cfg3 */
1836 .mpllb = { 0x409a, /* mpllb cfg0 */
1837 0x7d20, /* mpllb cfg1 */
1838 0xca06, /* mpllb cfg2 */
1839 0xbe40, /* mpllb cfg3 */
1840 0x0000, /* mpllb cfg4 */
1841 0x0000, /* mpllb cfg5 */
1842 0x2200, /* mpllb cfg6 */
1843 0x0001, /* mpllb cfg7 */
1844 0x5800, /* mpllb cfg8 */
1845 0x0000, /* mpllb cfg9 */
1846 0x0001, /* mpllb cfg10 */
1852 .tx = { 0xbe88, /* tx cfg0 */
1853 0x9800, /* tx cfg1 */
1854 0x0000, /* tx cfg2 */
1856 .cmn = { 0x0500, /* cmn cfg0*/
1857 0x0005, /* cmn cfg1 */
1858 0x0000, /* cmn cfg2 */
1859 0x0000, /* cmn cfg3 */
1861 .mpllb = { 0x009a, /* mpllb cfg0 */
1862 0x7d08, /* mpllb cfg1 */
1863 0xca06, /* mpllb cfg2 */
1864 0xbe40, /* mpllb cfg3 */
1865 0x0000, /* mpllb cfg4 */
1866 0x0000, /* mpllb cfg5 */
1867 0x2200, /* mpllb cfg6 */
1868 0x0001, /* mpllb cfg7 */
1869 0x5800, /* mpllb cfg8 */
1870 0x0000, /* mpllb cfg9 */
1871 0x0001, /* mpllb cfg10 */
1877 .tx = { 0xbe98, /* tx cfg0 */
1878 0x8800, /* tx cfg1 */
1879 0x0000, /* tx cfg2 */
1881 .cmn = { 0x0500, /* cmn cfg0*/
1882 0x0005, /* cmn cfg1 */
1883 0x0000, /* cmn cfg2 */
1884 0x0000, /* cmn cfg3 */
1886 .mpllb = { 0x309c, /* mpllb cfg0 */
1887 0x2110, /* mpllb cfg1 */
1888 0xca06, /* mpllb cfg2 */
1889 0xbe40, /* mpllb cfg3 */
1890 0x0000, /* mpllb cfg4 */
1891 0x0000, /* mpllb cfg5 */
1892 0x2200, /* mpllb cfg6 */
1893 0x0001, /* mpllb cfg7 */
1894 0x2000, /* mpllb cfg8 */
1895 0x0000, /* mpllb cfg9 */
1896 0x0004, /* mpllb cfg10 */
1902 .tx = { 0xbe98, /* tx cfg0 */
1903 0x8800, /* tx cfg1 */
1904 0x0000, /* tx cfg2 */
1906 .cmn = { 0x0500, /* cmn cfg0*/
1907 0x0005, /* cmn cfg1 */
1908 0x0000, /* cmn cfg2 */
1909 0x0000, /* cmn cfg3 */
1911 .mpllb = { 0x109c, /* mpllb cfg0 */
1912 0x2108, /* mpllb cfg1 */
1913 0xca06, /* mpllb cfg2 */
1914 0xbe40, /* mpllb cfg3 */
1915 0x0000, /* mpllb cfg4 */
1916 0x0000, /* mpllb cfg5 */
1917 0x2200, /* mpllb cfg6 */
1918 0x0001, /* mpllb cfg7 */
1919 0x2000, /* mpllb cfg8 */
1920 0x0000, /* mpllb cfg9 */
1921 0x0004, /* mpllb cfg10 */
1927 .tx = { 0xbe98, /* tx cfg0 */
1928 0x8800, /* tx cfg1 */
1929 0x0000, /* tx cfg2 */
1931 .cmn = { 0x0500, /* cmn cfg0*/
1932 0x0005, /* cmn cfg1 */
1933 0x0000, /* cmn cfg2 */
1934 0x0000, /* cmn cfg3 */
1936 .mpllb = { 0x10d0, /* mpllb cfg0 */
1937 0x2108, /* mpllb cfg1 */
1938 0x4a06, /* mpllb cfg2 */
1939 0xbe40, /* mpllb cfg3 */
1940 0x0000, /* mpllb cfg4 */
1941 0x0000, /* mpllb cfg5 */
1942 0x2200, /* mpllb cfg6 */
1943 0x0003, /* mpllb cfg7 */
1944 0x2aaa, /* mpllb cfg8 */
1945 0x0002, /* mpllb cfg9 */
1946 0x0004, /* mpllb cfg10 */
1952 .tx = { 0xbe98, /* tx cfg0 */
1953 0x8800, /* tx cfg1 */
1954 0x0000, /* tx cfg2 */
1956 .cmn = { 0x0500, /* cmn cfg0*/
1957 0x0005, /* cmn cfg1 */
1958 0x0000, /* cmn cfg2 */
1959 0x0000, /* cmn cfg3 */
1961 .mpllb = { 0x1104, /* mpllb cfg0 */
1962 0x2108, /* mpllb cfg1 */
1963 0x0a06, /* mpllb cfg2 */
1964 0xbe40, /* mpllb cfg3 */
1965 0x0000, /* mpllb cfg4 */
1966 0x0000, /* mpllb cfg5 */
1967 0x2200, /* mpllb cfg6 */
1968 0x0003, /* mpllb cfg7 */
1969 0x3555, /* mpllb cfg8 */
1970 0x0001, /* mpllb cfg9 */
1971 0x0004, /* mpllb cfg10 */
1977 .tx = { 0xbe98, /* tx cfg0 */
1978 0x8800, /* tx cfg1 */
1979 0x0000, /* tx cfg2 */
1981 .cmn = { 0x0500, /* cmn cfg0*/
1982 0x0005, /* cmn cfg1 */
1983 0x0000, /* cmn cfg2 */
1984 0x0000, /* cmn cfg3 */
1986 .mpllb = { 0x1138, /* mpllb cfg0 */
1987 0x2108, /* mpllb cfg1 */
1988 0x5486, /* mpllb cfg2 */
1989 0xfe40, /* mpllb cfg3 */
1990 0x0000, /* mpllb cfg4 */
1991 0x0000, /* mpllb cfg5 */
1992 0x2200, /* mpllb cfg6 */
1993 0x0001, /* mpllb cfg7 */
1994 0x4000, /* mpllb cfg8 */
1995 0x0000, /* mpllb cfg9 */
1996 0x0004, /* mpllb cfg10 */
2056 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
2066 for (i = 0; tables[i]; i++) { in intel_c10pll_calc_state_from_table()
2073 return 0; in intel_c10pll_calc_state_from_table()
2095 if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) in intel_c10pll_calc_state()
2105 return 0; in intel_c10pll_calc_state()
2122 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10pll_readout_hw_state()
2125 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
2128 pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
2129 pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
2141 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10_pll_program()
2145 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
2150 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2151 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2153 /* Custom width needs to be programmed to 0 for both the phy lanes */ in intel_c10_pll_program()
2158 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
2167 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_dump_hw_state()
2170 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; in intel_c10pll_dump_hw_state()
2189 drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, in intel_c10pll_dump_hw_state()
2193 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
2195 "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", in intel_c10pll_dump_hw_state()
2226 tx_misc = 0; in intel_c20_hdmi_tmds_tx_cgf_1()
2263 mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
2264 mpll_fracn_rem = multiplier & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
2279 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
2281 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2282 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
2283 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
2284 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2285 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2286 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
2297 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2298 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2305 return 0; in intel_c20_compute_hdmi_tmds_pll()
2345 if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0) in intel_c20pll_calc_state()
2346 return 0; in intel_c20pll_calc_state()
2353 for (i = 0; tables[i]; i++) { in intel_c20pll_calc_state()
2360 return 0; in intel_c20pll_calc_state()
2377 return state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20phy_use_mpllb()
2390 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2398 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2399 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2401 fb_clk_div4_en = 0; in intel_c20pll_calc_port_clock()
2408 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2411 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2417 frac = 0; in intel_c20pll_calc_port_clock()
2439 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2451 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2464 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2476 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2500 "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2501 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2503 "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2504 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2507 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) in intel_c20pll_dump_hw_state()
2508 drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2511 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) in intel_c20pll_dump_hw_state()
2512 drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2530 return 0; in intel_c20_get_dp_rate()
2545 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2547 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2549 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2557 return 0; in intel_c20_get_dp_rate()
2564 return 0; in intel_c20_get_hdmi_rate()
2577 return 0; in intel_c20_get_hdmi_rate()
2583 /* DP2.0 clock rates */ in is_dp2()
2620 return 0; in intel_get_c20_custom_width()
2633 cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); in intel_c20_pll_program()
2637 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. in intel_c20_pll_program()
2641 for (i = 0; i < 4; i++) in intel_c20_pll_program()
2642 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); in intel_c20_pll_program()
2648 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2660 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2673 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2684 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2711 is_hdmi_frl(port_clock) ? BIT(7) : 0, in intel_c20_pll_program()
2724 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); in intel_c20_pll_program()
2730 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_calc_port_clock()
2732 int tmpclk = 0; in intel_c10pll_calc_port_clock()
2734 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2760 u32 val = 0; in intel_program_port_clock_ctl()
2764 lane_reversal ? XELPDP_PORT_REVERSAL : 0); in intel_program_port_clock_ctl()
2777 /* DP2.0 10G and 20G rates enable MPLLA*/ in intel_program_port_clock_ctl()
2779 val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()
2781 val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()
2791 u32 val = 0; in intel_cx0_get_powerdown_update()
2792 int lane = 0; in intel_cx0_get_powerdown_update()
2802 u32 val = 0; in intel_cx0_get_powerdown_state()
2803 int lane = 0; in intel_cx0_get_powerdown_state()
2841 intel_cx0_get_powerdown_update(lane_mask), 0, in intel_cx0_powerdown_change_sequence()
2842 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) in intel_cx0_powerdown_change_sequence()
2860 XELPDP_PLL_LANE_STAGGERING_DELAY(0)); in intel_cx0_setup_powerdown()
2865 u32 val = 0; in intel_cx0_get_pclk_refclk_request()
2866 int lane = 0; in intel_cx0_get_pclk_refclk_request()
2876 u32 val = 0; in intel_cx0_get_pclk_refclk_ack()
2877 int lane = 0; in intel_cx0_get_pclk_refclk_ack()
2894 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) in intel_cx0_phy_lane_reset()
2895 : XELPDP_LANE_PIPE_RESET(0); in intel_cx0_phy_lane_reset()
2897 ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | in intel_cx0_phy_lane_reset()
2899 : XELPDP_LANE_PHY_CURRENT_STATUS(0); in intel_cx0_phy_lane_reset()
2904 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2914 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2926 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2935 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0); in intel_cx0_phy_lane_reset()
2955 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2960 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2962 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
2965 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2966 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
2969 for (i = 0; i < 4; i++) { in intel_cx0_program_phy_lane()
2978 disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, in intel_cx0_program_phy_lane()
2984 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2991 u32 val = 0; in intel_cx0_get_pclk_pll_request()
2992 int lane = 0; in intel_cx0_get_pclk_pll_request()
3002 u32 val = 0; in intel_cx0_get_pclk_pll_ack()
3003 int lane = 0; in intel_cx0_get_pclk_pll_ack()
3040 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000. in __intel_cx0pll_enable()
3080 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) in __intel_cx0pll_enable()
3168 u32 val = 0; in intel_mtl_tbt_pll_enable()
3204 100, 0, NULL)) in intel_mtl_tbt_pll_enable()
3235 * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This
3255 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, in intel_lnl_mac_transmit_lfps()
3258 for (i = 0; i < 4; i++) { in intel_lnl_mac_transmit_lfps()
3265 intel_cx0_rmw(encoder, lane_mask, PHY_CMN1_CONTROL(tx, 0), in intel_lnl_mac_transmit_lfps()
3304 * to "0" to disable PLL. in intel_cx0pll_disable()
3308 intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); in intel_cx0pll_disable()
3310 /* 4. Program DDI_CLK_VALFREQ to 0. */ in intel_cx0pll_disable()
3311 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
3314 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". in intel_cx0pll_disable()
3318 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, in intel_cx0pll_disable()
3319 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_disable()
3331 XELPDP_DDI_CLOCK_SELECT_MASK(display), 0); in intel_cx0pll_disable()
3333 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_cx0pll_disable()
3359 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. in intel_mtl_tbt_pll_disable()
3362 XELPDP_TBT_CLOCK_REQUEST, 0); in intel_mtl_tbt_pll_disable()
3364 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()
3366 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) in intel_mtl_tbt_pll_disable()
3381 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_mtl_tbt_pll_disable()
3383 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()
3384 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
3427 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { in intel_c10pll_state_verify()
3431 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3437 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3442 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3473 if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0) in mtl_compare_hw_state_c10()
3482 if (memcmp(&a->tx, &b->tx, sizeof(a->tx)) != 0) in mtl_compare_hw_state_c20()
3485 if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0) in mtl_compare_hw_state_c20()
3488 if (a->tx[0] & C20_PHY_USE_MPLLB) { in mtl_compare_hw_state_c20()
3489 if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0) in mtl_compare_hw_state_c20()
3492 if (memcmp(&a->mplla, &b->mplla, sizeof(a->mplla)) != 0) in mtl_compare_hw_state_c20()
3548 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { in intel_c20pll_state_verify()
3550 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3555 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { in intel_c20pll_state_verify()
3557 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3563 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { in intel_c20pll_state_verify()
3565 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3570 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { in intel_c20pll_state_verify()
3572 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3646 &pll_state) < 0) { in intel_cx0_pll_power_save_wa()