Lines Matching refs:control
172 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
177 if (!control) in __get_eeprom_i2c_addr()
190 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
199 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
203 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
205 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
208 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
213 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
215 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
220 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
222 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
227 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
260 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) in __write_table_header() argument
263 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_header()
267 __encode_table_header_to_buf(&control->tbl_hdr, buf); in __write_table_header()
272 control->i2c_address + in __write_table_header()
273 control->ras_header_offset, in __write_table_header()
316 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __write_table_ras_info() argument
318 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_ras_info()
328 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); in __write_table_ras_info()
333 control->i2c_address + in __write_table_ras_info()
334 control->ras_info_offset, in __write_table_ras_info()
353 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_hdr_byte_sum() argument
360 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); in __calc_hdr_byte_sum()
361 pp = (u8 *) &control->tbl_hdr; in __calc_hdr_byte_sum()
369 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_ras_info_byte_sum() argument
375 sz = sizeof(control->tbl_rai); in __calc_ras_info_byte_sum()
376 pp = (u8 *) &control->tbl_rai; in __calc_ras_info_byte_sum()
385 struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_correct_header_tag() argument
388 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_correct_header_tag()
400 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
403 res = __write_table_header(control); in amdgpu_ras_eeprom_correct_header_tag()
404 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
409 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_set_eeprom_table_version() argument
411 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_set_eeprom_table_version()
412 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_set_eeprom_table_version()
432 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_reset_table() argument
434 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_reset_table()
435 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_reset_table()
436 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in amdgpu_ras_eeprom_reset_table()
441 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
444 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_reset_table()
463 csum = __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
465 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
468 res = __write_table_header(control); in amdgpu_ras_eeprom_reset_table()
470 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_reset_table()
472 control->ras_num_recs = 0; in amdgpu_ras_eeprom_reset_table()
473 control->ras_fri = 0; in amdgpu_ras_eeprom_reset_table()
475 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); in amdgpu_ras_eeprom_reset_table()
477 control->bad_channel_bitmap = 0; in amdgpu_ras_eeprom_reset_table()
478 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); in amdgpu_ras_eeprom_reset_table()
481 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_reset_table()
483 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
489 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, in __encode_table_record_to_buf() argument
517 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, in __decode_table_record_from_buf() argument
587 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_write() argument
590 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_write()
598 control->i2c_address + in __amdgpu_ras_eeprom_write()
599 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_write()
619 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append_table() argument
623 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); in amdgpu_ras_eeprom_append_table()
636 __encode_table_record_to_buf(control, &record[i], pp); in amdgpu_ras_eeprom_append_table()
639 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_append_table()
640 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_append_table()
641 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_append_table()
673 a = control->ras_fri + control->ras_num_recs; in amdgpu_ras_eeprom_append_table()
675 if (b < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
676 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
677 } else if (a < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
680 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
681 g1 = b % control->ras_max_record_count + 1; in amdgpu_ras_eeprom_append_table()
682 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
685 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
690 if (g1 > control->ras_fri) in amdgpu_ras_eeprom_append_table()
691 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
693 a %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
694 b %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
698 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
701 if (b >= control->ras_fri) in amdgpu_ras_eeprom_append_table()
702 control->ras_fri = (b + 1) % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
710 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
712 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
715 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
720 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
723 control->ras_num_recs = 1 + (control->ras_max_record_count + b in amdgpu_ras_eeprom_append_table()
724 - control->ras_fri) in amdgpu_ras_eeprom_append_table()
725 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
732 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_update_header() argument
734 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_update_header()
743 control->ras_num_recs >= ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
746 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
747 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; in amdgpu_ras_eeprom_update_header()
748 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) { in amdgpu_ras_eeprom_update_header()
749 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; in amdgpu_ras_eeprom_update_header()
750 control->tbl_rai.health_percent = 0; in amdgpu_ras_eeprom_update_header()
760 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
761 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
763 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
765 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
766 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
767 control->tbl_hdr.checksum = 0; in amdgpu_ras_eeprom_update_header()
769 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
770 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); in amdgpu_ras_eeprom_update_header()
773 control->tbl_hdr.tbl_size); in amdgpu_ras_eeprom_update_header()
780 control->i2c_address + in amdgpu_ras_eeprom_update_header()
781 control->ras_record_offset, in amdgpu_ras_eeprom_update_header()
800 control->tbl_hdr.version == RAS_TABLE_VER_V2_1 && in amdgpu_ras_eeprom_update_header()
801 control->ras_num_recs < ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
802 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
803 control->ras_num_recs) * 100) / in amdgpu_ras_eeprom_update_header()
812 csum += __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_update_header()
813 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
814 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_update_header()
817 control->tbl_hdr.checksum = csum; in amdgpu_ras_eeprom_update_header()
818 res = __write_table_header(control); in amdgpu_ras_eeprom_update_header()
819 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) in amdgpu_ras_eeprom_update_header()
820 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_update_header()
839 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append() argument
843 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append()
852 } else if (num > control->ras_max_record_count) { in amdgpu_ras_eeprom_append()
854 num, control->ras_max_record_count); in amdgpu_ras_eeprom_append()
858 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
860 res = amdgpu_ras_eeprom_append_table(control, record, num); in amdgpu_ras_eeprom_append()
862 res = amdgpu_ras_eeprom_update_header(control); in amdgpu_ras_eeprom_append()
864 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_append()
866 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
880 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_read() argument
883 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_read()
891 control->i2c_address + in __amdgpu_ras_eeprom_read()
892 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_read()
922 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_read() argument
926 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_read()
938 } else if (num > control->ras_num_recs) { in amdgpu_ras_eeprom_read()
940 num, control->ras_num_recs); in amdgpu_ras_eeprom_read()
968 g0 = control->ras_fri + num - 1; in amdgpu_ras_eeprom_read()
969 g1 = g0 % control->ras_max_record_count; in amdgpu_ras_eeprom_read()
970 if (g0 < control->ras_max_record_count) { in amdgpu_ras_eeprom_read()
974 g0 = control->ras_max_record_count - control->ras_fri; in amdgpu_ras_eeprom_read()
978 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
979 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); in amdgpu_ras_eeprom_read()
983 res = __amdgpu_ras_eeprom_read(control, in amdgpu_ras_eeprom_read()
996 __decode_table_record_from_buf(control, &record[i], pp); in amdgpu_ras_eeprom_read()
999 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_read()
1000 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_read()
1001 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_read()
1007 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
1012 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_max_record_count() argument
1015 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_max_record_count()
1017 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_max_record_count()
1029 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read() local
1036 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
1040 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); in amdgpu_ras_debugfs_eeprom_size_read()
1077 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_table_size() argument
1080 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; in amdgpu_ras_debugfs_table_size()
1083 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_set_ret_size() argument
1085 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, in amdgpu_ras_debugfs_set_ret_size()
1090 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_set_ret_size()
1098 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; in amdgpu_ras_debugfs_table_read() local
1103 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1125 control->tbl_hdr.header, in amdgpu_ras_debugfs_table_read()
1126 control->tbl_hdr.version, in amdgpu_ras_debugfs_table_read()
1127 control->tbl_hdr.first_rec_offset, in amdgpu_ras_debugfs_table_read()
1128 control->tbl_hdr.tbl_size, in amdgpu_ras_debugfs_table_read()
1129 control->tbl_hdr.checksum); in amdgpu_ras_debugfs_table_read()
1155 data_len = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_table_read()
1171 for ( ; size > 0 && s < control->ras_num_recs; s++) { in amdgpu_ras_debugfs_table_read()
1172 u32 ai = RAS_RI_TO_AI(control, s); in amdgpu_ras_debugfs_table_read()
1175 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); in amdgpu_ras_debugfs_table_read()
1178 __decode_table_record_from_buf(control, &record, dare); in amdgpu_ras_debugfs_table_read()
1181 RAS_INDEX_TO_OFFSET(control, ai), in amdgpu_ras_debugfs_table_read()
1203 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1213 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_table_read() local
1220 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_table_read()
1256 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) in __verify_ras_table_checksum() argument
1258 struct amdgpu_device *adev = to_amdgpu_device(control); in __verify_ras_table_checksum()
1262 if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) in __verify_ras_table_checksum()
1265 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1268 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1277 control->i2c_address + in __verify_ras_table_checksum()
1278 control->ras_header_offset, in __verify_ras_table_checksum()
1297 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __read_table_ras_info() argument
1299 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in __read_table_ras_info()
1300 struct amdgpu_device *adev = to_amdgpu_device(control); in __read_table_ras_info()
1315 control->i2c_address + control->ras_info_offset, in __read_table_ras_info()
1330 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_init() argument
1332 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_init()
1334 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_init()
1347 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_init()
1350 control->ras_header_offset = RAS_HDR_START; in amdgpu_ras_eeprom_init()
1351 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; in amdgpu_ras_eeprom_init()
1352 mutex_init(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_init()
1356 control->i2c_address + control->ras_header_offset, in amdgpu_ras_eeprom_init()
1366 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); in amdgpu_ras_eeprom_init()
1367 control->ras_record_offset = RAS_RECORD_START_V2_1; in amdgpu_ras_eeprom_init()
1368 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; in amdgpu_ras_eeprom_init()
1370 control->ras_num_recs = RAS_NUM_RECS(hdr); in amdgpu_ras_eeprom_init()
1371 control->ras_record_offset = RAS_RECORD_START; in amdgpu_ras_eeprom_init()
1372 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; in amdgpu_ras_eeprom_init()
1374 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); in amdgpu_ras_eeprom_init()
1378 control->ras_num_recs); in amdgpu_ras_eeprom_init()
1381 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_init()
1386 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_init()
1393 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_init()
1395 control->ras_num_recs, in amdgpu_ras_eeprom_init()
1400 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_init()
1405 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_init()
1409 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { in amdgpu_ras_eeprom_init()
1419 control->ras_num_recs, in amdgpu_ras_eeprom_init()
1421 res = amdgpu_ras_eeprom_correct_header_tag(control, in amdgpu_ras_eeprom_init()
1425 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_init()
1434 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_init()
1440 res = amdgpu_ras_eeprom_reset_table(control); in amdgpu_ras_eeprom_init()