Lines Matching full:ohci
3 * Driver for OHCI 1394 controllers
42 #include "ohci.h"
53 #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args) argument
54 #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args) argument
96 struct fw_ohci *ohci; member
127 struct fw_ohci *ohci; member
298 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci) in has_reboot_by_cycle_timer_read_quirk() argument
300 return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ); in has_reboot_by_cycle_timer_read_quirk()
330 #define has_reboot_by_cycle_timer_read_quirk(ohci) false argument
404 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) in reg_write() argument
406 writel(data, ohci->registers + offset); in reg_write()
409 static inline u32 reg_read(const struct fw_ohci *ohci, int offset) in reg_read() argument
411 return readl(ohci->registers + offset); in reg_read()
414 static inline void flush_writes(const struct fw_ohci *ohci) in flush_writes() argument
417 reg_read(ohci, OHCI1394_Version); in flush_writes()
422 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
426 static int read_phy_reg(struct fw_ohci *ohci, int addr) in read_phy_reg() argument
431 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); in read_phy_reg()
433 val = reg_read(ohci, OHCI1394_PhyControl); in read_phy_reg()
447 ohci_err(ohci, "failed to read phy reg %d\n", addr); in read_phy_reg()
453 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) in write_phy_reg() argument
457 reg_write(ohci, OHCI1394_PhyControl, in write_phy_reg()
460 val = reg_read(ohci, OHCI1394_PhyControl); in write_phy_reg()
470 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val); in write_phy_reg()
476 static int update_phy_reg(struct fw_ohci *ohci, int addr, in update_phy_reg() argument
479 int ret = read_phy_reg(ohci, addr); in update_phy_reg()
490 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); in update_phy_reg()
493 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) in read_paged_phy_reg() argument
497 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); in read_paged_phy_reg()
501 return read_phy_reg(ohci, addr); in read_paged_phy_reg()
506 struct fw_ohci *ohci = fw_ohci(card); in ohci_read_phy_reg() local
508 guard(mutex)(&ohci->phy_reg_mutex); in ohci_read_phy_reg()
510 return read_phy_reg(ohci, addr); in ohci_read_phy_reg()
516 struct fw_ohci *ohci = fw_ohci(card); in ohci_update_phy_reg() local
518 guard(mutex)(&ohci->phy_reg_mutex); in ohci_update_phy_reg()
520 return update_phy_reg(ohci, addr, clear_bits, set_bits); in ohci_update_phy_reg()
538 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); in ar_context_link_page()
543 struct device *dev = ctx->ohci->card.device; in ar_context_release()
564 struct fw_ohci *ohci = ctx->ohci; in ar_context_abort() local
566 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { in ar_context_abort()
567 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); in ar_context_abort()
568 flush_writes(ohci); in ar_context_abort()
570 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg); in ar_context_abort()
652 dma_sync_single_for_cpu(ctx->ohci->card.device, ctx->dma_addrs[i], PAGE_SIZE, in ar_sync_buffers_for_cpu()
657 dma_sync_single_for_cpu(ctx->ohci->card.device, ctx->dma_addrs[i], in ar_sync_buffers_for_cpu()
667 static bool has_be_header_quirk(const struct fw_ohci *ohci) in has_be_header_quirk() argument
669 return !!(ohci->quirks & QUIRK_BE_HEADERS); in has_be_header_quirk()
677 static bool has_be_header_quirk(const struct fw_ohci *ohci) in has_be_header_quirk() argument
685 struct fw_ohci *ohci = ctx->ohci; in handle_ar_packet() local
690 p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci)); in handle_ar_packet()
691 p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci)); in handle_ar_packet()
692 p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci)); in handle_ar_packet()
704 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); in handle_ar_packet()
713 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci)); in handle_ar_packet()
738 status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci)); in handle_ar_packet()
744 p.generation = ohci->request_generation; in handle_ar_packet()
754 * The OHCI bus reset handler synthesizes a PHY packet with in handle_ar_packet()
767 if (!(ohci->quirks & QUIRK_RESET_PACKET)) in handle_ar_packet()
768 ohci->request_generation = (p.header[2] >> 16) & 0xff; in handle_ar_packet()
769 } else if (ctx == &ohci->ar_request_ctx) { in handle_ar_packet()
770 fw_core_handle_request(&ohci->card, &p); in handle_ar_packet()
772 fw_core_handle_response(&ohci->card, &p); in handle_ar_packet()
798 dma_sync_single_for_device(ctx->ohci->card.device, ctx->dma_addrs[i], PAGE_SIZE, in ar_recycle_buffers()
846 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, in ar_context_init() argument
849 struct device *dev = ohci->card.device; in ar_context_init()
857 ctx->ohci = ohci; in ar_context_init()
860 // Retrieve noncontiguous pages. The descriptors for 1394 OHCI AR DMA contexts have a set in ar_context_init()
903 ctx->descriptors = ohci->misc_buffer + descriptors_offset; in ar_context_init()
904 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; in ar_context_init()
929 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); in ar_context_run()
930 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); in ar_context_run()
979 guard(spinlock_irqsave)(&ctx->ohci->lock); in context_retire_descriptors()
1003 * context. Must be called with ohci->lock held.
1018 desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC); in context_add_buffer()
1039 static int context_init(struct context *ctx, struct fw_ohci *ohci, in context_init() argument
1042 ctx->ohci = ohci; in context_init()
1073 struct fw_card *card = &ctx->ohci->card; in context_release()
1082 /* Must be called with ohci->lock held */
1116 struct fw_ohci *ohci = ctx->ohci; in context_run() local
1118 reg_write(ohci, COMMAND_PTR(ctx->regs), in context_run()
1120 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); in context_run()
1121 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); in context_run()
1123 flush_writes(ohci); in context_run()
1151 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) && in context_append()
1164 struct fw_ohci *ohci = ctx->ohci; in context_stop() local
1168 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); in context_stop()
1172 reg = reg_read(ohci, CONTROL_SET(ctx->regs)); in context_stop()
1179 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg); in context_stop()
1195 struct fw_ohci *ohci = context->ohci; in at_context_queue_packet() local
1232 if (ctx == &ohci->at_response_ctx) { in at_context_queue_packet()
1283 payload_bus = dma_map_single(ohci->card.device, in at_context_queue_packet()
1287 if (dma_mapping_error(ohci->card.device, payload_bus)) { in at_context_queue_packet()
1313 if (ohci->generation != packet->generation) { in at_context_queue_packet()
1315 dma_unmap_single(ohci->card.device, payload_bus, in at_context_queue_packet()
1324 reg_write(ohci, CONTROL_SET(context->regs), CONTEXT_WAKE); in at_context_queue_packet()
1359 struct fw_ohci *ohci = ctx->context.ohci; in handle_at_packet() local
1375 dma_unmap_single(ohci->card.device, packet->payload_bus, in handle_at_packet()
1432 fw_card_get(&ohci->card); in handle_at_packet()
1433 dev = device_find_child(ohci->card.device, (const void *)params, find_fw_device); in handle_at_packet()
1434 fw_card_put(&ohci->card); in handle_at_packet()
1450 packet->callback(packet, &ohci->card, packet->ack); in handle_at_packet()
1455 static u32 get_cycle_time(struct fw_ohci *ohci);
1457 static void handle_local_rom(struct fw_ohci *ohci, in handle_local_rom() argument
1478 (void *) ohci->config_rom + i, length); in handle_local_rom()
1482 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); in handle_local_rom()
1483 fw_core_handle_response(&ohci->card, &response); in handle_local_rom()
1486 static void handle_local_lock(struct fw_ohci *ohci, in handle_local_lock() argument
1513 reg_write(ohci, OHCI1394_CSRData, lock_data); in handle_local_lock()
1514 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); in handle_local_lock()
1515 reg_write(ohci, OHCI1394_CSRControl, sel); in handle_local_lock()
1518 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { in handle_local_lock()
1519 lock_old = cpu_to_be32(reg_read(ohci, in handle_local_lock()
1527 ohci_err(ohci, "swap not done (CSR lock timeout)\n"); in handle_local_lock()
1532 response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); in handle_local_lock()
1533 fw_core_handle_response(&ohci->card, &response); in handle_local_lock()
1538 struct fw_ohci *ohci = ctx->context.ohci; in handle_local_request() local
1541 if (ctx == &ohci->at_request_ctx) { in handle_local_request()
1543 packet->callback(packet, &ohci->card, packet->ack); in handle_local_request()
1551 handle_local_rom(ohci, packet, csr); in handle_local_request()
1557 handle_local_lock(ohci, packet, csr); in handle_local_request()
1560 if (ctx == &ohci->at_request_ctx) in handle_local_request()
1561 fw_core_handle_request(&ohci->card, packet); in handle_local_request()
1563 fw_core_handle_response(&ohci->card, packet); in handle_local_request()
1567 if (ctx == &ohci->at_response_ctx) { in handle_local_request()
1569 packet->callback(packet, &ohci->card, packet->ack); in handle_local_request()
1575 struct fw_ohci *ohci = ctx->context.ohci; in at_context_transmit() local
1579 spin_lock_irqsave(&ohci->lock, flags); in at_context_transmit()
1581 if (async_header_get_destination(packet->header) == ohci->node_id && in at_context_transmit()
1582 ohci->generation == packet->generation) { in at_context_transmit()
1583 spin_unlock_irqrestore(&ohci->lock, flags); in at_context_transmit()
1586 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); in at_context_transmit()
1593 spin_unlock_irqrestore(&ohci->lock, flags); in at_context_transmit()
1597 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); in at_context_transmit()
1599 packet->callback(packet, &ohci->card, packet->ack); in at_context_transmit()
1603 static void detect_dead_context(struct fw_ohci *ohci, in detect_dead_context() argument
1627 ctl = reg_read(ohci, CONTROL_SET(regs)); in detect_dead_context()
1629 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n", in detect_dead_context()
1633 static void handle_dead_contexts(struct fw_ohci *ohci) in handle_dead_contexts() argument
1638 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase); in handle_dead_contexts()
1639 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase); in handle_dead_contexts()
1640 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase); in handle_dead_contexts()
1641 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase); in handle_dead_contexts()
1643 if (!(ohci->it_context_support & (1 << i))) in handle_dead_contexts()
1646 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i)); in handle_dead_contexts()
1649 if (!(ohci->ir_context_support & (1 << i))) in handle_dead_contexts()
1652 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i)); in handle_dead_contexts()
1683 static u32 get_cycle_time(struct fw_ohci *ohci) in get_cycle_time() argument
1690 if (has_reboot_by_cycle_timer_read_quirk(ohci)) in get_cycle_time()
1693 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); in get_cycle_time()
1695 if (ohci->quirks & QUIRK_CYCLE_TIMER) { in get_cycle_time()
1698 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); in get_cycle_time()
1702 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); in get_cycle_time()
1722 static u32 update_bus_time(struct fw_ohci *ohci) in update_bus_time() argument
1724 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; in update_bus_time()
1726 if (unlikely(!ohci->bus_time_running)) { in update_bus_time()
1727 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds); in update_bus_time()
1728 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) | in update_bus_time()
1730 ohci->bus_time_running = true; in update_bus_time()
1733 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) in update_bus_time()
1734 ohci->bus_time += 0x40; in update_bus_time()
1736 return ohci->bus_time | cycle_time_seconds; in update_bus_time()
1739 static int get_status_for_port(struct fw_ohci *ohci, int port_index, in get_status_for_port() argument
1744 scoped_guard(mutex, &ohci->phy_reg_mutex) { in get_status_for_port()
1745 reg = write_phy_reg(ohci, 7, port_index); in get_status_for_port()
1749 reg = read_phy_reg(ohci, 8); in get_status_for_port()
1772 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id, in get_self_id_pos() argument
1779 u32 entry = ohci->self_id_buffer[i]; in get_self_id_pos()
1790 static int detect_initiated_reset(struct fw_ohci *ohci, bool *is_initiated_reset) in detect_initiated_reset() argument
1794 guard(mutex)(&ohci->phy_reg_mutex); in detect_initiated_reset()
1797 reg = write_phy_reg(ohci, 7, 0xe0); in detect_initiated_reset()
1801 reg = read_phy_reg(ohci, 8); in detect_initiated_reset()
1807 reg = write_phy_reg(ohci, 8, reg); in detect_initiated_reset()
1812 reg = read_phy_reg(ohci, 12); in detect_initiated_reset()
1827 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count) in find_and_insert_self_id() argument
1839 reg = reg_read(ohci, OHCI1394_NodeID); in find_and_insert_self_id()
1841 ohci_notice(ohci, in find_and_insert_self_id()
1847 reg = ohci_read_phy_reg(&ohci->card, 4); in find_and_insert_self_id()
1852 reg = ohci_read_phy_reg(&ohci->card, 1); in find_and_insert_self_id()
1860 err = get_status_for_port(ohci, i, &status); in find_and_insert_self_id()
1867 err = detect_initiated_reset(ohci, &is_initiated_reset); in find_and_insert_self_id()
1872 pos = get_self_id_pos(ohci, self_id, self_id_count); in find_and_insert_self_id()
1874 memmove(&(ohci->self_id_buffer[pos+1]), in find_and_insert_self_id()
1875 &(ohci->self_id_buffer[pos]), in find_and_insert_self_id()
1876 (self_id_count - pos) * sizeof(*ohci->self_id_buffer)); in find_and_insert_self_id()
1877 ohci->self_id_buffer[pos] = self_id; in find_and_insert_self_id()
1885 struct fw_ohci *ohci = data; in handle_selfid_complete_event() local
1892 reg = reg_read(ohci, OHCI1394_NodeID); in handle_selfid_complete_event()
1894 ohci_notice(ohci, in handle_selfid_complete_event()
1899 ohci_notice(ohci, "malconfigured bus\n"); in handle_selfid_complete_event()
1902 ohci->node_id = reg & (OHCI1394_NodeID_busNumber | in handle_selfid_complete_event()
1906 if (!(ohci->is_root && is_new_root)) in handle_selfid_complete_event()
1907 reg_write(ohci, OHCI1394_LinkControlSet, in handle_selfid_complete_event()
1909 ohci->is_root = is_new_root; in handle_selfid_complete_event()
1911 reg = reg_read(ohci, OHCI1394_SelfIDCount); in handle_selfid_complete_event()
1913 ohci_notice(ohci, "self ID receive error\n"); in handle_selfid_complete_event()
1917 trace_self_id_complete(ohci->card.index, reg, ohci->self_id, has_be_header_quirk(ohci)); in handle_selfid_complete_event()
1928 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg); in handle_selfid_complete_event()
1932 quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci)); in handle_selfid_complete_event()
1937 u32 id = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci)); in handle_selfid_complete_event()
1938 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci)); in handle_selfid_complete_event()
1949 ohci_notice(ohci, "ignoring spurious self IDs\n"); in handle_selfid_complete_event()
1954 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n", in handle_selfid_complete_event()
1958 ohci->self_id_buffer[j] = id; in handle_selfid_complete_event()
1961 if (ohci->quirks & QUIRK_TI_SLLZ059) { in handle_selfid_complete_event()
1962 self_id_count = find_and_insert_self_id(ohci, self_id_count); in handle_selfid_complete_event()
1964 ohci_notice(ohci, in handle_selfid_complete_event()
1971 ohci_notice(ohci, "no self IDs\n"); in handle_selfid_complete_event()
1981 * will read out inconsistent data. The OHCI specification in handle_selfid_complete_event()
1990 reg = reg_read(ohci, OHCI1394_SelfIDCount); in handle_selfid_complete_event()
1993 ohci_notice(ohci, "new bus reset, discarding self ids\n"); in handle_selfid_complete_event()
1998 scoped_guard(spinlock_irq, &ohci->lock) { in handle_selfid_complete_event()
1999 ohci->generation = -1; // prevent AT packet queueing in handle_selfid_complete_event()
2000 context_stop(&ohci->at_request_ctx.context); in handle_selfid_complete_event()
2001 context_stop(&ohci->at_response_ctx.context); in handle_selfid_complete_event()
2005 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent in handle_selfid_complete_event()
2007 * Some OHCI 1.1 controllers (JMicron) apparently require this too. in handle_selfid_complete_event()
2009 at_context_flush(&ohci->at_request_ctx); in handle_selfid_complete_event()
2010 at_context_flush(&ohci->at_response_ctx); in handle_selfid_complete_event()
2012 scoped_guard(spinlock_irq, &ohci->lock) { in handle_selfid_complete_event()
2013 ohci->generation = generation; in handle_selfid_complete_event()
2014 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); in handle_selfid_complete_event()
2015 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); in handle_selfid_complete_event()
2017 if (ohci->quirks & QUIRK_RESET_PACKET) in handle_selfid_complete_event()
2018 ohci->request_generation = generation; in handle_selfid_complete_event()
2025 if (ohci->next_config_rom != NULL) { in handle_selfid_complete_event()
2026 if (ohci->next_config_rom != ohci->config_rom) { in handle_selfid_complete_event()
2027 free_rom = ohci->config_rom; in handle_selfid_complete_event()
2028 free_rom_bus = ohci->config_rom_bus; in handle_selfid_complete_event()
2030 ohci->config_rom = ohci->next_config_rom; in handle_selfid_complete_event()
2031 ohci->config_rom_bus = ohci->next_config_rom_bus; in handle_selfid_complete_event()
2032 ohci->next_config_rom = NULL; in handle_selfid_complete_event()
2037 reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->config_rom[2])); in handle_selfid_complete_event()
2038 ohci->config_rom[0] = ohci->next_header; in handle_selfid_complete_event()
2039 reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(ohci->next_header)); in handle_selfid_complete_event()
2043 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); in handle_selfid_complete_event()
2044 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); in handle_selfid_complete_event()
2049 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus); in handle_selfid_complete_event()
2051 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, in handle_selfid_complete_event()
2052 self_id_count, ohci->self_id_buffer, in handle_selfid_complete_event()
2053 ohci->csr_state_setclear_abdicate); in handle_selfid_complete_event()
2054 ohci->csr_state_setclear_abdicate = false; in handle_selfid_complete_event()
2061 struct fw_ohci *ohci = data; in irq_handler() local
2065 event = reg_read(ohci, OHCI1394_IntEventClear); in irq_handler()
2072 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) in irq_handler()
2074 reg_write(ohci, OHCI1394_IntEventClear, in irq_handler()
2076 trace_irqs(ohci->card.index, event); in irq_handler()
2080 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset); in irq_handler()
2083 queue_work(ohci->card.async_wq, &ohci->ar_request_ctx.work); in irq_handler()
2086 queue_work(ohci->card.async_wq, &ohci->ar_response_ctx.work); in irq_handler()
2089 queue_work(ohci->card.async_wq, &ohci->at_request_ctx.work); in irq_handler()
2092 queue_work(ohci->card.async_wq, &ohci->at_response_ctx.work); in irq_handler()
2095 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); in irq_handler()
2096 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); in irq_handler()
2100 fw_iso_context_schedule_flush_completions(&ohci->ir_context_list[i].base); in irq_handler()
2106 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); in irq_handler()
2107 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); in irq_handler()
2111 fw_iso_context_schedule_flush_completions(&ohci->it_context_list[i].base); in irq_handler()
2117 ohci_err(ohci, "register access failure\n"); in irq_handler()
2120 reg_read(ohci, OHCI1394_PostedWriteAddressHi); in irq_handler()
2121 reg_read(ohci, OHCI1394_PostedWriteAddressLo); in irq_handler()
2122 reg_write(ohci, OHCI1394_IntEventClear, in irq_handler()
2124 dev_err_ratelimited(ohci->card.device, "PCI posted write error\n"); in irq_handler()
2128 dev_notice_ratelimited(ohci->card.device, "isochronous cycle too long\n"); in irq_handler()
2129 reg_write(ohci, OHCI1394_LinkControlSet, in irq_handler()
2140 dev_notice_ratelimited(ohci->card.device, "isochronous cycle inconsistent\n"); in irq_handler()
2144 handle_dead_contexts(ohci); in irq_handler()
2147 guard(spinlock)(&ohci->lock); in irq_handler()
2148 update_bus_time(ohci); in irq_handler()
2150 flush_writes(ohci); in irq_handler()
2158 static int software_reset(struct fw_ohci *ohci) in software_reset() argument
2163 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); in software_reset()
2165 val = reg_read(ohci, OHCI1394_HCControlSet); in software_reset()
2187 static int configure_1394a_enhancements(struct fw_ohci *ohci) in configure_1394a_enhancements() argument
2193 if (!(reg_read(ohci, OHCI1394_HCControlSet) & in configure_1394a_enhancements()
2199 ret = read_phy_reg(ohci, 2); in configure_1394a_enhancements()
2203 ret = read_paged_phy_reg(ohci, 1, 8); in configure_1394a_enhancements()
2210 if (ohci->quirks & QUIRK_NO_1394A) in configure_1394a_enhancements()
2221 ret = update_phy_reg(ohci, 5, clear, set); in configure_1394a_enhancements()
2229 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); in configure_1394a_enhancements()
2232 reg_write(ohci, OHCI1394_HCControlClear, in configure_1394a_enhancements()
2238 static int probe_tsb41ba3d(struct fw_ohci *ohci) in probe_tsb41ba3d() argument
2244 reg = read_phy_reg(ohci, 2); in probe_tsb41ba3d()
2251 reg = read_paged_phy_reg(ohci, 1, i + 10); in probe_tsb41ba3d()
2263 struct fw_ohci *ohci = fw_ohci(card); in ohci_enable() local
2267 ret = software_reset(ohci); in ohci_enable()
2269 ohci_err(ohci, "failed to reset ohci card\n"); in ohci_enable()
2286 reg_write(ohci, OHCI1394_HCControlSet, in ohci_enable()
2289 flush_writes(ohci); in ohci_enable()
2293 lps = reg_read(ohci, OHCI1394_HCControlSet) & in ohci_enable()
2298 ohci_err(ohci, "failed to set Link Power Status\n"); in ohci_enable()
2302 if (ohci->quirks & QUIRK_TI_SLLZ059) { in ohci_enable()
2303 ret = probe_tsb41ba3d(ohci); in ohci_enable()
2307 ohci_notice(ohci, "local TSB41BA3D phy\n"); in ohci_enable()
2309 ohci->quirks &= ~QUIRK_TI_SLLZ059; in ohci_enable()
2312 reg_write(ohci, OHCI1394_HCControlClear, in ohci_enable()
2315 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); in ohci_enable()
2316 reg_write(ohci, OHCI1394_LinkControlSet, in ohci_enable()
2320 reg_write(ohci, OHCI1394_ATRetries, in ohci_enable()
2326 ohci->bus_time_running = false; in ohci_enable()
2329 if (ohci->ir_context_support & (1 << i)) in ohci_enable()
2330 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i), in ohci_enable()
2333 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; in ohci_enable()
2335 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, in ohci_enable()
2341 reg_write(ohci, OHCI1394_FairnessControl, 0x3f); in ohci_enable()
2342 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; in ohci_enable()
2343 reg_write(ohci, OHCI1394_FairnessControl, 0); in ohci_enable()
2344 card->priority_budget_implemented = ohci->pri_req_max != 0; in ohci_enable()
2346 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16); in ohci_enable()
2347 reg_write(ohci, OHCI1394_IntEventClear, ~0); in ohci_enable()
2348 reg_write(ohci, OHCI1394_IntMaskClear, ~0); in ohci_enable()
2350 ret = configure_1394a_enhancements(ohci); in ohci_enable()
2366 * OHCI requires that ConfigROMhdr and BusOptions have valid in ohci_enable()
2379 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, in ohci_enable()
2380 &ohci->next_config_rom_bus, GFP_KERNEL); in ohci_enable()
2381 if (ohci->next_config_rom == NULL) in ohci_enable()
2384 copy_config_rom(ohci->next_config_rom, config_rom, length); in ohci_enable()
2390 ohci->next_config_rom = ohci->config_rom; in ohci_enable()
2391 ohci->next_config_rom_bus = ohci->config_rom_bus; in ohci_enable()
2394 ohci->next_header = ohci->next_config_rom[0]; in ohci_enable()
2395 ohci->next_config_rom[0] = 0; in ohci_enable()
2396 reg_write(ohci, OHCI1394_ConfigROMhdr, 0); in ohci_enable()
2397 reg_write(ohci, OHCI1394_BusOptions, in ohci_enable()
2398 be32_to_cpu(ohci->next_config_rom[2])); in ohci_enable()
2399 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); in ohci_enable()
2401 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); in ohci_enable()
2414 reg_write(ohci, OHCI1394_IntMaskSet, irqs); in ohci_enable()
2416 reg_write(ohci, OHCI1394_HCControlSet, in ohci_enable()
2420 reg_write(ohci, OHCI1394_LinkControlSet, in ohci_enable()
2424 ar_context_run(&ohci->ar_request_ctx); in ohci_enable()
2425 ar_context_run(&ohci->ar_response_ctx); in ohci_enable()
2427 flush_writes(ohci); in ohci_enable()
2430 fw_schedule_bus_reset(&ohci->card, false, true); in ohci_enable()
2438 struct fw_ohci *ohci = pci_get_drvdata(pdev); in ohci_disable() local
2443 if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS)) in ohci_disable()
2446 reg_write(ohci, OHCI1394_IntMaskClear, ~0); in ohci_disable()
2447 flush_writes(ohci); in ohci_disable()
2452 flush_work(&ohci->ar_request_ctx.work); in ohci_disable()
2453 flush_work(&ohci->ar_response_ctx.work); in ohci_disable()
2454 flush_work(&ohci->at_request_ctx.work); in ohci_disable()
2455 flush_work(&ohci->at_response_ctx.work); in ohci_disable()
2457 for (i = 0; i < ohci->n_ir; ++i) { in ohci_disable()
2458 if (!(ohci->ir_context_mask & BIT(i))) in ohci_disable()
2459 flush_work(&ohci->ir_context_list[i].base.work); in ohci_disable()
2461 for (i = 0; i < ohci->n_it; ++i) { in ohci_disable()
2462 if (!(ohci->it_context_mask & BIT(i))) in ohci_disable()
2463 flush_work(&ohci->it_context_list[i].base.work); in ohci_disable()
2466 at_context_flush(&ohci->at_request_ctx); in ohci_disable()
2467 at_context_flush(&ohci->at_response_ctx); in ohci_disable()
2473 struct fw_ohci *ohci; in ohci_set_config_rom() local
2477 ohci = fw_ohci(card); in ohci_set_config_rom()
2480 * When the OHCI controller is enabled, the config rom update in ohci_set_config_rom()
2482 * section 5.5.6 in the OHCI specification. in ohci_set_config_rom()
2484 * The OHCI controller caches the new config rom address in a in ohci_set_config_rom()
2502 * We use ohci->lock to avoid racing with the code that sets in ohci_set_config_rom()
2503 * ohci->next_config_rom to NULL (see handle_selfid_complete_event). in ohci_set_config_rom()
2506 next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, in ohci_set_config_rom()
2511 scoped_guard(spinlock_irq, &ohci->lock) { in ohci_set_config_rom()
2513 // into the ohci->next_config_rom and then mark the local variable as null so that in ohci_set_config_rom()
2518 if (ohci->next_config_rom == NULL) { in ohci_set_config_rom()
2519 ohci->next_config_rom = next_config_rom; in ohci_set_config_rom()
2520 ohci->next_config_rom_bus = next_config_rom_bus; in ohci_set_config_rom()
2524 copy_config_rom(ohci->next_config_rom, config_rom, length); in ohci_set_config_rom()
2526 ohci->next_header = config_rom[0]; in ohci_set_config_rom()
2527 ohci->next_config_rom[0] = 0; in ohci_set_config_rom()
2529 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); in ohci_set_config_rom()
2534 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom, in ohci_set_config_rom()
2541 * mappings in the bus reset work item, since the OHCI in ohci_set_config_rom()
2546 fw_schedule_bus_reset(&ohci->card, true, true); in ohci_set_config_rom()
2553 struct fw_ohci *ohci = fw_ohci(card); in ohci_send_request() local
2555 at_context_transmit(&ohci->at_request_ctx, packet); in ohci_send_request()
2560 struct fw_ohci *ohci = fw_ohci(card); in ohci_send_response() local
2562 at_context_transmit(&ohci->at_response_ctx, packet); in ohci_send_response()
2567 struct fw_ohci *ohci = fw_ohci(card); in ohci_cancel_packet() local
2568 struct at_context *ctx = &ohci->at_request_ctx; in ohci_cancel_packet()
2581 dma_unmap_single(ohci->card.device, packet->payload_bus, in ohci_cancel_packet()
2588 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci)); in ohci_cancel_packet()
2590 packet->callback(packet, &ohci->card, packet->ack); in ohci_cancel_packet()
2601 struct fw_ohci *ohci = fw_ohci(card); in ohci_enable_phys_dma() local
2612 guard(spinlock_irqsave)(&ohci->lock); in ohci_enable_phys_dma()
2614 if (ohci->generation != generation) in ohci_enable_phys_dma()
2624 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); in ohci_enable_phys_dma()
2626 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); in ohci_enable_phys_dma()
2628 flush_writes(ohci); in ohci_enable_phys_dma()
2635 struct fw_ohci *ohci = fw_ohci(card); in ohci_read_csr() local
2641 if (ohci->is_root && in ohci_read_csr()
2642 (reg_read(ohci, OHCI1394_LinkControlSet) & in ohci_read_csr()
2647 if (ohci->csr_state_setclear_abdicate) in ohci_read_csr()
2653 return reg_read(ohci, OHCI1394_NodeID) << 16; in ohci_read_csr()
2656 return get_cycle_time(ohci); in ohci_read_csr()
2664 guard(spinlock_irqsave)(&ohci->lock); in ohci_read_csr()
2665 return update_bus_time(ohci); in ohci_read_csr()
2668 value = reg_read(ohci, OHCI1394_ATRetries); in ohci_read_csr()
2672 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | in ohci_read_csr()
2673 (ohci->pri_req_max << 8); in ohci_read_csr()
2683 struct fw_ohci *ohci = fw_ohci(card); in ohci_write_csr() local
2687 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { in ohci_write_csr()
2688 reg_write(ohci, OHCI1394_LinkControlClear, in ohci_write_csr()
2690 flush_writes(ohci); in ohci_write_csr()
2693 ohci->csr_state_setclear_abdicate = false; in ohci_write_csr()
2697 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { in ohci_write_csr()
2698 reg_write(ohci, OHCI1394_LinkControlSet, in ohci_write_csr()
2700 flush_writes(ohci); in ohci_write_csr()
2703 ohci->csr_state_setclear_abdicate = true; in ohci_write_csr()
2707 reg_write(ohci, OHCI1394_NodeID, value >> 16); in ohci_write_csr()
2708 flush_writes(ohci); in ohci_write_csr()
2712 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); in ohci_write_csr()
2713 reg_write(ohci, OHCI1394_IntEventSet, in ohci_write_csr()
2715 flush_writes(ohci); in ohci_write_csr()
2720 guard(spinlock_irqsave)(&ohci->lock); in ohci_write_csr()
2721 ohci->bus_time = (update_bus_time(ohci) & 0x40) | (value & ~0x7f); in ohci_write_csr()
2727 reg_write(ohci, OHCI1394_ATRetries, value); in ohci_write_csr()
2728 flush_writes(ohci); in ohci_write_csr()
2732 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); in ohci_write_csr()
2733 flush_writes(ohci); in ohci_write_csr()
2800 dma_sync_single_range_for_cpu(context->ohci->card.device, in handle_ir_packet_per_buffer()
2839 dma_sync_single_range_for_cpu(context->ohci->card.device, in handle_ir_buffer_fill()
2859 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device, in flush_ir_buffer_fill()
2899 dma_sync_single_range_for_cpu(context->ohci->card.device, in sync_it_packet_for_cpu()
2946 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) in set_multichannel_mask() argument
2950 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); in set_multichannel_mask()
2951 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); in set_multichannel_mask()
2952 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); in set_multichannel_mask()
2953 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); in set_multichannel_mask()
2954 ohci->mc_channels = channels; in set_multichannel_mask()
2960 struct fw_ohci *ohci = fw_ohci(card); in ohci_allocate_iso_context() local
2968 scoped_guard(spinlock_irq, &ohci->lock) { in ohci_allocate_iso_context()
2971 mask = &ohci->it_context_mask; in ohci_allocate_iso_context()
2977 ctx = &ohci->it_context_list[index]; in ohci_allocate_iso_context()
2982 channels = &ohci->ir_context_channels; in ohci_allocate_iso_context()
2983 mask = &ohci->ir_context_mask; in ohci_allocate_iso_context()
2990 ctx = &ohci->ir_context_list[index]; in ohci_allocate_iso_context()
2995 mask = &ohci->ir_context_mask; in ohci_allocate_iso_context()
2997 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; in ohci_allocate_iso_context()
2999 ohci->mc_allocated = true; in ohci_allocate_iso_context()
3002 ctx = &ohci->ir_context_list[index]; in ohci_allocate_iso_context()
3026 ret = context_init(&ctx->context, ohci, regs, callback); in ohci_allocate_iso_context()
3034 set_multichannel_mask(ohci, 0); in ohci_allocate_iso_context()
3040 scoped_guard(spinlock_irq, &ohci->lock) { in ohci_allocate_iso_context()
3047 ohci->mc_allocated = false; in ohci_allocate_iso_context()
3060 struct fw_ohci *ohci = ctx->context.ohci; in ohci_start_iso() local
3070 index = ctx - ohci->it_context_list; in ohci_start_iso()
3076 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); in ohci_start_iso()
3077 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); in ohci_start_iso()
3085 index = ctx - ohci->ir_context_list; in ohci_start_iso()
3092 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); in ohci_start_iso()
3093 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); in ohci_start_iso()
3094 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); in ohci_start_iso()
3108 struct fw_ohci *ohci = fw_ohci(base->card); in ohci_stop_iso() local
3114 index = ctx - ohci->it_context_list; in ohci_stop_iso()
3115 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); in ohci_stop_iso()
3120 index = ctx - ohci->ir_context_list; in ohci_stop_iso()
3121 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); in ohci_stop_iso()
3124 flush_writes(ohci); in ohci_stop_iso()
3132 struct fw_ohci *ohci = fw_ohci(base->card); in ohci_free_iso_context() local
3144 guard(spinlock_irqsave)(&ohci->lock); in ohci_free_iso_context()
3148 index = ctx - ohci->it_context_list; in ohci_free_iso_context()
3149 ohci->it_context_mask |= 1 << index; in ohci_free_iso_context()
3153 index = ctx - ohci->ir_context_list; in ohci_free_iso_context()
3154 ohci->ir_context_mask |= 1 << index; in ohci_free_iso_context()
3155 ohci->ir_context_channels |= 1ULL << base->channel; in ohci_free_iso_context()
3159 index = ctx - ohci->ir_context_list; in ohci_free_iso_context()
3160 ohci->ir_context_mask |= 1 << index; in ohci_free_iso_context()
3161 ohci->ir_context_channels |= ohci->mc_channels; in ohci_free_iso_context()
3162 ohci->mc_channels = 0; in ohci_free_iso_context()
3163 ohci->mc_allocated = false; in ohci_free_iso_context()
3170 struct fw_ohci *ohci = fw_ohci(base->card); in ohci_set_iso_channels() local
3175 guard(spinlock_irqsave)(&ohci->lock); in ohci_set_iso_channels()
3178 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { in ohci_set_iso_channels()
3179 *channels = ohci->ir_context_channels; in ohci_set_iso_channels()
3182 set_multichannel_mask(ohci, *channels); in ohci_set_iso_channels()
3191 static void __maybe_unused ohci_resume_iso_dma(struct fw_ohci *ohci) in ohci_resume_iso_dma() argument
3196 for (i = 0 ; i < ohci->n_ir ; i++) { in ohci_resume_iso_dma()
3197 ctx = &ohci->ir_context_list[i]; in ohci_resume_iso_dma()
3202 for (i = 0 ; i < ohci->n_it ; i++) { in ohci_resume_iso_dma()
3203 ctx = &ohci->it_context_list[i]; in ohci_resume_iso_dma()
3290 dma_sync_single_range_for_device(ctx->context.ohci->card.device, in queue_iso_transmit()
3318 struct device *device = ctx->context.ohci->card.device; in queue_iso_packet_per_buffer()
3326 * The OHCI controller puts the isochronous header and trailer in the in queue_iso_packet_per_buffer()
3436 dma_sync_single_range_for_device(ctx->context.ohci->card.device, in queue_iso_buffer_fill()
3457 guard(spinlock_irqsave)(&ctx->context.ohci->lock); in ohci_queue_iso()
3476 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); in ohci_flush_queue_iso()
3563 struct fw_ohci *ohci = pci_get_drvdata(pdev); in release_ohci() local
3567 ar_context_release(&ohci->ar_response_ctx); in release_ohci()
3568 ar_context_release(&ohci->ar_request_ctx); in release_ohci()
3570 dev_notice(dev, "removed fw-ohci device\n"); in release_ohci()
3576 struct fw_ohci *ohci; in pci_probe() local
3586 ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL); in pci_probe()
3587 if (ohci == NULL) in pci_probe()
3589 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); in pci_probe()
3590 pci_set_drvdata(dev, ohci); in pci_probe()
3592 devres_add(&dev->dev, ohci); in pci_probe()
3596 dev_err(&dev->dev, "failed to enable OHCI hardware\n"); in pci_probe()
3603 spin_lock_init(&ohci->lock); in pci_probe()
3604 mutex_init(&ohci->phy_reg_mutex); in pci_probe()
3608 ohci_err(ohci, "invalid MMIO resource\n"); in pci_probe()
3612 ohci->registers = pcim_iomap_region(dev, 0, ohci_driver_name); in pci_probe()
3613 if (IS_ERR(ohci->registers)) { in pci_probe()
3614 ohci_err(ohci, "request and map MMIO resource unavailable\n"); in pci_probe()
3624 ohci->quirks = ohci_quirks[i].flags; in pci_probe()
3628 ohci->quirks = param_quirks; in pci_probe()
3631 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ; in pci_probe()
3640 ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus, in pci_probe()
3642 if (!ohci->misc_buffer) in pci_probe()
3645 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, in pci_probe()
3650 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, in pci_probe()
3655 err = context_init(&ohci->at_request_ctx.context, ohci, in pci_probe()
3659 INIT_WORK(&ohci->at_request_ctx.work, ohci_at_context_work); in pci_probe()
3661 err = context_init(&ohci->at_response_ctx.context, ohci, in pci_probe()
3665 INIT_WORK(&ohci->at_response_ctx.work, ohci_at_context_work); in pci_probe()
3667 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); in pci_probe()
3668 ohci->ir_context_channels = ~0ULL; in pci_probe()
3669 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); in pci_probe()
3670 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); in pci_probe()
3671 ohci->ir_context_mask = ohci->ir_context_support; in pci_probe()
3672 ohci->n_ir = hweight32(ohci->ir_context_mask); in pci_probe()
3673 …ohci->ir_context_list = devm_kcalloc(&dev->dev, ohci->n_ir, sizeof(struct iso_context), GFP_KERNEL… in pci_probe()
3674 if (!ohci->ir_context_list) in pci_probe()
3677 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); in pci_probe()
3678 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); in pci_probe()
3680 if (!ohci->it_context_support) { in pci_probe()
3681 ohci_notice(ohci, "overriding IsoXmitIntMask\n"); in pci_probe()
3682 ohci->it_context_support = 0xf; in pci_probe()
3684 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); in pci_probe()
3685 ohci->it_context_mask = ohci->it_context_support; in pci_probe()
3686 ohci->n_it = hweight32(ohci->it_context_mask); in pci_probe()
3687 …ohci->it_context_list = devm_kcalloc(&dev->dev, ohci->n_it, sizeof(struct iso_context), GFP_KERNEL… in pci_probe()
3688 if (!ohci->it_context_list) in pci_probe()
3691 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2; in pci_probe()
3692 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; in pci_probe()
3694 bus_options = reg_read(ohci, OHCI1394_BusOptions); in pci_probe()
3697 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | in pci_probe()
3698 reg_read(ohci, OHCI1394_GUIDLo); in pci_probe()
3701 if (!(ohci->quirks & QUIRK_NO_MSI)) in pci_probe()
3716 ohci); in pci_probe()
3718 ohci_err(ohci, "failed to allocate interrupt %d\n", irq); in pci_probe()
3722 err = fw_card_add(&ohci->card, max_receive, link_speed, guid, ohci->n_it + ohci->n_ir); in pci_probe()
3726 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; in pci_probe()
3727 ohci_notice(ohci, in pci_probe()
3728 "added OHCI v%x.%x device as card %d, " in pci_probe()
3730 version >> 16, version & 0xff, ohci->card.index, in pci_probe()
3731 ohci->n_ir, ohci->n_it, ohci->quirks, in pci_probe()
3732 reg_read(ohci, OHCI1394_PhyUpperBound) ? in pci_probe()
3738 free_irq(irq, ohci); in pci_probe()
3747 struct fw_ohci *ohci = pci_get_drvdata(dev); in pci_remove() local
3750 fw_core_remove_card(&ohci->card); in pci_remove()
3752 software_reset(ohci); in pci_remove()
3756 free_irq(irq, ohci); in pci_remove()
3759 dev_notice(&dev->dev, "removing fw-ohci device\n"); in pci_remove()
3765 struct fw_ohci *ohci = pci_get_drvdata(pdev); in pci_suspend() local
3767 software_reset(ohci); in pci_suspend()
3777 struct fw_ohci *ohci = pci_get_drvdata(pdev); in pci_resume() local
3783 if (!reg_read(ohci, OHCI1394_GUIDLo) && in pci_resume()
3784 !reg_read(ohci, OHCI1394_GUIDHi)) { in pci_resume()
3785 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); in pci_resume()
3786 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); in pci_resume()
3789 err = ohci_enable(&ohci->card, NULL, 0); in pci_resume()
3793 ohci_resume_iso_dma(ohci); in pci_resume()
3829 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");