Lines Matching +full:reg +full:- +full:40 +full:h
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
11 #include <linux/module.h>
12 #include <linux/ctype.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pci_ids.h>
16 #include <linux/slab.h>
17 #include <linux/mmzone.h>
18 #include <linux/edac.h>
19 #include <linux/bitfield.h>
20 #include <asm/cpu_device_id.h>
21 #include <asm/msr.h>
22 #include "edac_module.h"
23 #include "mce_amd.h"
105 * PCI-defined configuration space registers
119 * Function 1 - Address Map
131 * F15 M30h D18F1x2[4C:40]
135 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
136 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
137 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
140 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
141 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
142 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
145 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
157 * Function 2 - DRAM controller
166 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
167 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
174 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
175 #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) argument
189 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
190 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
192 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
194 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
195 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
204 * Function 3 - Misc Control
219 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
220 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
225 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
285 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
304 u32 dimm_cfg; /* DIMM Configuration reg */
305 u32 umc_cfg; /* Configuration reg */
306 u32 sdp_ctrl; /* SDP Control reg */
307 u32 ecc_ctrl; /* DRAM ECC Control reg */
308 u32 umc_cap_hi; /* Capabilities High reg */
317 * first introduced with Family 19h Model 10h.
338 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
339 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
340 u32 dchr0; /* DRAM Configuration High DCT0 reg */
341 u32 dchr1; /* DRAM Configuration High DCT1 reg */
344 u32 dhar; /* DRAM Hoist reg */
345 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
346 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
351 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
359 u32 online_spare; /* On-Line spare Reg */
377 * NOTE: Don't use this for Family 17h and later.
387 ERR_NODE = -1,
388 ERR_CSROW = -2,
389 ERR_CHANNEL = -3,
390 ERR_SYND = -4,
391 ERR_NORM_ADDR = -5,
412 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; in get_dram_base()
417 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; in get_dram_base()
422 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; in get_dram_limit()
427 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; in get_dram_limit()
437 if (pvt->fam == 0x15 && pvt->model >= 0x30) in dct_sel_interleave_addr()
438 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | in dct_sel_interleave_addr()
439 ((pvt->dct_sel_lo >> 6) & 0x3); in dct_sel_interleave_addr()
441 return ((pvt)->dct_sel_lo >> 6) & 0x3; in dct_sel_interleave_addr()
444 * per-node ECC settings descriptor
499 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dram_intlv_en()
501 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); in dram_intlv_en()
504 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; in dram_intlv_en()
509 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dhar_valid()
511 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); in dhar_valid()
514 return (pvt)->dhar & BIT(0); in dhar_valid()
519 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dct_sel_baseaddr()
521 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); in dct_sel_baseaddr()
524 return (pvt)->dct_sel_lo & 0xFFFFF800; in dct_sel_baseaddr()