Lines Matching +full:3 +full:_chan
15 #define EDMA_CR_ERGA BIT(3)
29 #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
40 #define EDMA_TCD_CSR_D_REQ BIT(3)
77 #define EDMA_V3_CH_ERR_NCE BIT(3)
210 #define FSL_EDMA_DRV_WRAP_IO BIT(3)
332 #define fsl_edma_get_tcd(_chan, _tcd, _field) \ argument
333 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
343 #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \ argument
344 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? \
355 #define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field) \ argument
357 if (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64) \