Lines Matching +full:sun6i +full:- +full:a31 +full:- +full:ahb1 +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
47 req->k = 1; in sun4i_get_pll1_factors()
49 req->k = 0; in sun4i_get_pll1_factors()
53 req->p = 3; in sun4i_get_pll1_factors()
55 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ in sun4i_get_pll1_factors()
57 req->p = 2; in sun4i_get_pll1_factors()
60 * of divs between 40-62 */ in sun4i_get_pll1_factors()
62 req->p = 1; in sun4i_get_pll1_factors()
66 req->p = 0; in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
75 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
86 u32 freq_mhz = req->rate / 1000000; in sun6i_a31_get_pll1_factors()
87 u32 parent_freq_mhz = req->parent_rate / 1000000; in sun6i_a31_get_pll1_factors()
101 req->rate = freq_mhz * 1000000; in sun6i_a31_get_pll1_factors()
105 req->k = 3; in sun6i_a31_get_pll1_factors()
108 req->k = 2; in sun6i_a31_get_pll1_factors()
111 req->k = 1; in sun6i_a31_get_pll1_factors()
114 req->k = 0; in sun6i_a31_get_pll1_factors()
125 req->m = 2; in sun6i_a31_get_pll1_factors()
131 req->m = 3; in sun6i_a31_get_pll1_factors()
134 req->m = 1; in sun6i_a31_get_pll1_factors()
137 req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz) in sun6i_a31_get_pll1_factors()
138 - 1; in sun6i_a31_get_pll1_factors()
144 if ((req->n + 1) > 31 && (req->m + 1) > 1) { in sun6i_a31_get_pll1_factors()
145 req->n = (req->n + 1) / 2 - 1; in sun6i_a31_get_pll1_factors()
146 req->m = (req->m + 1) / 2 - 1; in sun6i_a31_get_pll1_factors()
151 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
162 div = req->rate / 6000000; in sun8i_a23_get_pll1_factors()
163 req->rate = 6000000 * div; in sun8i_a23_get_pll1_factors()
166 req->m = 0; in sun8i_a23_get_pll1_factors()
169 if (req->rate >= 768000000 || req->rate == 42000000 || in sun8i_a23_get_pll1_factors()
170 req->rate == 54000000) in sun8i_a23_get_pll1_factors()
171 req->k = 1; in sun8i_a23_get_pll1_factors()
173 req->k = 0; in sun8i_a23_get_pll1_factors()
177 req->p = 2; in sun8i_a23_get_pll1_factors()
180 * of divs between 40-62 */ in sun8i_a23_get_pll1_factors()
182 req->p = 1; in sun8i_a23_get_pll1_factors()
186 req->p = 0; in sun8i_a23_get_pll1_factors()
189 div <<= req->p; in sun8i_a23_get_pll1_factors()
190 div /= (req->k + 1); in sun8i_a23_get_pll1_factors()
191 req->n = div / 4 - 1; in sun8i_a23_get_pll1_factors()
195 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
206 div = req->rate / req->parent_rate; in sun4i_get_pll5_factors()
207 req->rate = req->parent_rate * div; in sun4i_get_pll5_factors()
210 req->k = 0; in sun4i_get_pll5_factors()
212 req->k = 1; in sun4i_get_pll5_factors()
214 req->k = 2; in sun4i_get_pll5_factors()
216 req->k = 3; in sun4i_get_pll5_factors()
218 req->n = DIV_ROUND_UP(div, (req->k + 1)); in sun4i_get_pll5_factors()
222 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
233 div = req->rate / req->parent_rate; in sun6i_a31_get_pll6_factors()
234 req->rate = req->parent_rate * div; in sun6i_a31_get_pll6_factors()
236 req->k = div / 32; in sun6i_a31_get_pll6_factors()
237 if (req->k > 3) in sun6i_a31_get_pll6_factors()
238 req->k = 3; in sun6i_a31_get_pll6_factors()
240 req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1; in sun6i_a31_get_pll6_factors()
244 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
254 if (req->parent_rate < req->rate) in sun5i_a13_get_ahb_factors()
255 req->rate = req->parent_rate; in sun5i_a13_get_ahb_factors()
261 if (req->rate < 8000) in sun5i_a13_get_ahb_factors()
262 req->rate = 8000; in sun5i_a13_get_ahb_factors()
263 if (req->rate > 300000000) in sun5i_a13_get_ahb_factors()
264 req->rate = 300000000; in sun5i_a13_get_ahb_factors()
266 div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate)); in sun5i_a13_get_ahb_factors()
272 req->rate = req->parent_rate >> div; in sun5i_a13_get_ahb_factors()
274 req->p = div; in sun5i_a13_get_ahb_factors()
280 * sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB
296 if (req->parent_rate && req->rate > req->parent_rate) in sun6i_get_ahb1_factors()
297 req->rate = req->parent_rate; in sun6i_get_ahb1_factors()
299 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_get_ahb1_factors()
301 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
302 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) { in sun6i_get_ahb1_factors()
318 req->rate = (req->parent_rate / calcm) >> calcp; in sun6i_get_ahb1_factors()
319 req->p = calcp; in sun6i_get_ahb1_factors()
320 req->m = calcm - 1; in sun6i_get_ahb1_factors()
324 * sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and
329 req->rate = req->parent_rate; in sun6i_ahb1_recalc()
331 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
332 if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) in sun6i_ahb1_recalc()
333 req->rate /= req->m + 1; in sun6i_ahb1_recalc()
336 req->rate >>= req->p; in sun6i_ahb1_recalc()
340 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
350 if (req->parent_rate < req->rate) in sun4i_get_apb1_factors()
351 req->rate = req->parent_rate; in sun4i_get_apb1_factors()
353 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_get_apb1_factors()
368 calcm = (div >> calcp) - 1; in sun4i_get_apb1_factors()
370 req->rate = (req->parent_rate >> calcp) / (calcm + 1); in sun4i_get_apb1_factors()
371 req->m = calcm; in sun4i_get_apb1_factors()
372 req->p = calcp; in sun4i_get_apb1_factors()
379 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
390 if (req->rate > req->parent_rate) in sun7i_a20_get_out_factors()
391 req->rate = req->parent_rate; in sun7i_a20_get_out_factors()
393 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun7i_a20_get_out_factors()
406 req->rate = (req->parent_rate >> calcp) / calcm; in sun7i_a20_get_out_factors()
407 req->m = calcm - 1; in sun7i_a20_get_out_factors()
408 req->p = calcp; in sun7i_a20_get_out_factors()
412 * sunxi_factors_clk_setup() - Setup function for factor clocks
563 pr_err("Could not get registers for factors-clk: %pOFn\n", in sunxi_factors_clk_setup()
575 CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk",
582 CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk",
589 CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk",
596 CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk",
603 CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk",
610 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
617 CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk",
624 CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk",
629 * sunxi_mux_clk_setup() - Setup function for muxes
655 const char *clk_name = node->name; in sunxi_mux_clk_setup()
662 pr_err("Could not map registers for mux-clk: %pOF\n", node); in sunxi_mux_clk_setup()
667 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_mux_clk_setup()
668 pr_err("%s: could not read clock-output-names from \"%pOF\"\n", in sunxi_mux_clk_setup()
675 data->shift, SUNXI_MUX_GATE_WIDTH, in sunxi_mux_clk_setup()
702 CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk",
709 CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk",
716 CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk",
721 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
779 const char *clk_name = node->name; in sunxi_divider_clk_setup()
785 pr_err("Could not map registers for mux-clk: %pOF\n", node); in sunxi_divider_clk_setup()
791 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_divider_clk_setup()
792 pr_err("%s: could not read clock-output-names from \"%pOF\"\n", in sunxi_divider_clk_setup()
798 reg, data->shift, data->width, in sunxi_divider_clk_setup()
799 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, in sunxi_divider_clk_setup()
800 data->table, &clk_lock); in sunxi_divider_clk_setup()
830 CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk",
837 CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk",
844 CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk",
851 CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
876 u8 pow; /* is it power-of-two based? */
922 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
926 * | ___divisor 1---|----> to consumer
927 * parent >--| pll___/___divisor 2---|----> to consumer
944 struct factors_data factors = *data->factors; in sunxi_divs_clk_setup()
951 if (data->ndivs) in sunxi_divs_clk_setup()
952 ndivs = data->ndivs; in sunxi_divs_clk_setup()
956 if (data->div[i].self) { in sunxi_divs_clk_setup()
957 of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
962 /* If we don't have a .self clk use the first output-name up to '_' */ in sunxi_divs_clk_setup()
966 of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
970 derived_name = kstrndup(clk_name, endp - clk_name, in sunxi_divs_clk_setup()
990 pr_err("Could not map registers for divs-clk: %pOF\n", node); in sunxi_divs_clk_setup()
1002 clk_data->clks = clks; in sunxi_divs_clk_setup()
1009 if (of_property_read_string_index(node, "clock-output-names", in sunxi_divs_clk_setup()
1014 if (data->div[i].self) { in sunxi_divs_clk_setup()
1015 clk_data->clks[i] = pclk; in sunxi_divs_clk_setup()
1024 if (data->div[i].gate) { in sunxi_divs_clk_setup()
1029 gate->reg = reg; in sunxi_divs_clk_setup()
1030 gate->bit_idx = data->div[i].gate; in sunxi_divs_clk_setup()
1031 gate->lock = &clk_lock; in sunxi_divs_clk_setup()
1033 gate_hw = &gate->hw; in sunxi_divs_clk_setup()
1037 if (data->div[i].fixed) { in sunxi_divs_clk_setup()
1042 fix_factor->mult = 1; in sunxi_divs_clk_setup()
1043 fix_factor->div = data->div[i].fixed; in sunxi_divs_clk_setup()
1045 rate_hw = &fix_factor->hw; in sunxi_divs_clk_setup()
1052 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; in sunxi_divs_clk_setup()
1054 divider->reg = reg; in sunxi_divs_clk_setup()
1055 divider->shift = data->div[i].shift; in sunxi_divs_clk_setup()
1056 divider->width = SUNXI_DIVISOR_WIDTH; in sunxi_divs_clk_setup()
1057 divider->flags = flags; in sunxi_divs_clk_setup()
1058 divider->lock = &clk_lock; in sunxi_divs_clk_setup()
1059 divider->table = data->div[i].table; in sunxi_divs_clk_setup()
1061 rate_hw = ÷r->hw; in sunxi_divs_clk_setup()
1072 (data->div[i].critical ? in sunxi_divs_clk_setup()
1075 WARN_ON(IS_ERR(clk_data->clks[i])); in sunxi_divs_clk_setup()
1079 clk_data->clk_num = i; in sunxi_divs_clk_setup()
1103 CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk",
1110 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1117 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
1121 * sun6i display
1129 if (req->rate > req->parent_rate) in sun6i_display_factors()
1130 req->rate = req->parent_rate; in sun6i_display_factors()
1132 m = DIV_ROUND_UP(req->parent_rate, req->rate); in sun6i_display_factors()
1134 req->rate = req->parent_rate / m; in sun6i_display_factors()
1135 req->m = m - 1; in sun6i_display_factors()
1155 CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk",