Lines Matching +full:sun8i +full:- +full:r40 +full:- +full:can
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-r40.h"
37 .hw.init = CLK_HW_INIT("pll-cpu",
49 * With sigma-delta modulation for fractional-N on the audio PLL,
51 * can no longer be used, as the audio codec requests the exact clock
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
88 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
101 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
120 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
130 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
131 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
138 .hw.init = CLK_HW_INIT("pll-periph0-sata",
139 "pll-periph0",
154 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
160 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
184 .hw.init = CLK_HW_INIT("pll-sata", "osc24M",
190 static const char * const pll_sata_out_parents[] = { "pll-sata",
191 "pll-periph0-sata" };
192 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
199 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
214 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
223 static const char * const pll_mipi_parents[] = { "pll-video0" };
233 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
241 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
254 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
263 "pll-cpu", "pll-cpu" };
270 "axi", "pll-periph0" };
306 "pll-periph0-2x",
307 "pll-periph0-2x" };
314 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
318 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
320 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
322 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
324 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
326 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
328 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
330 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
332 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
334 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
336 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
338 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
340 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
342 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
344 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
346 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
348 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
350 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
352 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
354 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
356 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
358 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
360 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
363 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
365 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
367 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
369 static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
371 static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
373 static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
375 static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
377 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
379 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
381 static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
383 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
385 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
387 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
389 static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
391 static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
393 static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
395 static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
397 static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
399 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
401 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
403 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
405 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
407 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
410 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
412 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
414 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
416 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
418 static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
420 static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
422 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
424 static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
426 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
428 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
430 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
433 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
435 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
437 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
439 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
445 static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
447 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
449 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
451 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
453 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
455 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
457 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
459 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
461 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
463 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
465 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
467 static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
469 static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
472 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
489 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
490 "pll-periph1" };
526 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
534 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
535 "pll-periph1-2x" };
571 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
572 "pll-audio-2x", "pll-audio" };
604 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
614 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
616 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
618 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
620 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
622 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
624 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
627 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
628 "pll-periph1", "osc32k" };
643 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
647 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
649 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
651 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
653 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
655 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
657 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
659 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
662 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
669 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
670 "pll-video0-2x", "pll-video1-2x",
671 "pll-mipi" };
672 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
674 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
676 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
679 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
683 static const char * const deinterlace_parents[] = { "pll-periph0",
684 "pll-periph1" };
689 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
690 "pll-periph1" };
691 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
694 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
695 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
698 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
701 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
704 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
709 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
714 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
724 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
725 "pll-ddr0" };
733 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
734 "pll-periph0" };
735 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
743 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
744 "pll-video0-2x", "pll-video1-2x" };
754 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
968 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
971 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
974 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
977 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
980 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
983 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
986 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
989 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
1280 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1320 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_r40_ccu_probe()
1325 /* Force PLL-MIPI to MIPI mode */ in sun8i_r40_ccu_probe()
1343 regmap = devm_regmap_init_mmio(&pdev->dev, reg, in sun8i_r40_ccu_probe()
1348 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_r40_ccu_desc); in sun8i_r40_ccu_probe()
1363 { .compatible = "allwinner,sun8i-r40-ccu" },
1371 .name = "sun8i-r40-ccu",
1379 MODULE_DESCRIPTION("Support for the Allwinner R40 CCU");