Lines Matching +full:0 +full:x2d0
33 .m = _SUNXI_CCU_DIV(0, 2),
36 .reg = 0x000,
56 #define SUN8I_R40_PLL_AUDIO_REG 0x008
59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
64 "osc24M", 0x008,
66 0, 5, /* M */
68 0x284, BIT(31),
74 "osc24M", 0x0010,
78 0, 4, /* M */
81 270000000, /* frac rate 0 */
89 "osc24M", 0x0018,
91 0, 4, /* M */
94 270000000, /* frac rate 0 */
102 "osc24M", 0x020,
105 0, 2, /* M */
118 .reg = 0x028,
128 .div = _SUNXI_CCU_DIV(0, 2),
136 .reg = 0x028,
140 &ccu_div_ops, 0),
152 .reg = 0x02c,
161 "osc24M", 0x030,
165 0, 4, /* M */
168 270000000, /* frac rate 0 */
179 .m = _SUNXI_CCU_DIV(0, 2),
182 .reg = 0x034,
193 pll_sata_out_parents, 0x034,
200 "osc24M", 0x038,
202 0, 4, /* M */
205 270000000, /* frac rate 0 */
221 #define SUN8I_R40_PLL_MIPI_REG 0x040
229 .m = _SUNXI_CCU_DIV(0, 4),
232 .reg = 0x040,
242 "osc24M", 0x048,
244 0, 4, /* M */
247 270000000, /* frac rate 0 */
255 "osc24M", 0x04c,
257 0, 2, /* M */
265 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
267 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
286 .reg = 0x054,
291 0),
296 { .val = 0, .div = 2 },
303 0x054, 8, 2, apb1_div_table, 0);
308 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
309 0, 5, /* M */
312 0);
315 0x060, BIT(1), 0);
317 0x060, BIT(5), 0);
319 0x060, BIT(6), 0);
321 0x060, BIT(8), 0);
323 0x060, BIT(9), 0);
325 0x060, BIT(10), 0);
327 0x060, BIT(11), 0);
329 0x060, BIT(13), 0);
331 0x060, BIT(14), 0);
333 0x060, BIT(17), 0);
335 0x060, BIT(18), 0);
337 0x060, BIT(19), 0);
339 0x060, BIT(20), 0);
341 0x060, BIT(21), 0);
343 0x060, BIT(22), 0);
345 0x060, BIT(23), 0);
347 0x060, BIT(24), 0);
349 0x060, BIT(25), 0);
351 0x060, BIT(26), 0);
353 0x060, BIT(27), 0);
355 0x060, BIT(28), 0);
357 0x060, BIT(29), 0);
359 0x060, BIT(30), 0);
361 0x060, BIT(31), 0);
364 0x064, BIT(0), 0);
366 0x064, BIT(2), 0);
368 0x064, BIT(5), 0);
370 0x064, BIT(8), 0);
372 0x064, BIT(9), 0);
374 0x064, BIT(10), 0);
376 0x064, BIT(11), 0);
378 0x064, BIT(12), 0);
380 0x064, BIT(13), 0);
382 0x064, BIT(14), 0);
384 0x064, BIT(15), 0);
386 0x064, BIT(17), 0);
388 0x064, BIT(20), 0);
390 0x064, BIT(21), 0);
392 0x064, BIT(22), 0);
394 0x064, BIT(23), 0);
396 0x064, BIT(24), 0);
398 0x064, BIT(25), 0);
400 0x064, BIT(26), 0);
402 0x064, BIT(27), 0);
404 0x064, BIT(28), 0);
406 0x064, BIT(29), 0);
408 0x064, BIT(30), 0);
411 0x068, BIT(0), 0);
413 0x068, BIT(1), 0);
415 0x068, BIT(2), 0);
417 0x068, BIT(5), 0);
419 0x068, BIT(6), 0);
421 0x068, BIT(7), 0);
423 0x068, BIT(8), 0);
425 0x068, BIT(10), 0);
427 0x068, BIT(12), 0);
429 0x068, BIT(13), 0);
431 0x068, BIT(14), 0);
434 0x06c, BIT(0), 0);
436 0x06c, BIT(1), 0);
438 0x06c, BIT(2), 0);
440 0x06c, BIT(3), 0);
446 0x06c, BIT(4), 0);
448 0x06c, BIT(5), 0);
450 0x06c, BIT(6), 0);
452 0x06c, BIT(7), 0);
454 0x06c, BIT(15), 0);
456 0x06c, BIT(16), 0);
458 0x06c, BIT(17), 0);
460 0x06c, BIT(18), 0);
462 0x06c, BIT(19), 0);
464 0x06c, BIT(20), 0);
466 0x06c, BIT(21), 0);
468 0x06c, BIT(22), 0);
470 0x06c, BIT(23), 0);
473 0x070, BIT(7), 0);
478 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
481 .reg = 0x074,
485 0),
491 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
492 0, 4, /* M */
496 0);
498 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
499 0, 4, /* M */
503 0);
505 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
506 0, 4, /* M */
510 0);
512 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
513 0, 4, /* M */
517 0);
519 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
520 0, 4, /* M */
524 0);
527 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
528 0, 4, /* M */
532 0);
536 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
537 0, 4, /* M */
541 0);
543 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
544 0, 4, /* M */
548 0);
550 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
551 0, 4, /* M */
555 0);
557 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
558 0, 4, /* M */
562 0);
564 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
565 0, 4, /* M */
569 0);
574 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
577 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
580 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
583 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
586 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
589 static const u8 keypad_table[] = { 0, 2 };
592 .m = _SUNXI_CCU_DIV(0, 5),
596 .reg = 0x0c4,
600 0),
606 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
610 * We will force them to 0 (12M divided from 48M).
612 #define SUN8I_R40_USB_CLK_REG 0x0cc
615 0x0cc, BIT(8), 0);
617 0x0cc, BIT(9), 0);
619 0x0cc, BIT(10), 0);
621 0x0cc, BIT(16), 0);
623 0x0cc, BIT(17), 0);
625 0x0cc, BIT(18), 0);
629 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
630 0, 4, /* M */
634 0);
636 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
637 0, 4, /* M */
641 0);
645 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
648 0x100, BIT(0), 0);
650 0x100, BIT(1), 0);
652 0x100, BIT(2), 0);
654 0x100, BIT(3), 0);
656 0x100, BIT(4), 0);
658 0x100, BIT(5), 0);
660 0x100, BIT(6), 0);
664 0x104, 0, 4, 24, 3, BIT(31),
667 0x108, 0, 4, 24, 3, BIT(31), 0);
673 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
675 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
677 0x118, 0, 4, 24, 3, BIT(31),
680 0x11c, 0, 4, 24, 3, BIT(31),
686 deinterlace_parents, 0x124, 0, 4, 24, 3,
687 BIT(31), 0);
692 0x130, 0, 5, 8, 3, BIT(15), 0);
696 0x134, 16, 4, 24, 3, BIT(31), 0);
699 0x134, 0, 5, 8, 3, BIT(15), 0);
702 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
705 0x140, BIT(31), CLK_SET_RATE_PARENT);
707 0x144, BIT(31), 0);
711 0x150, 0, 4, 24, 2, BIT(31),
715 0x154, BIT(31), 0);
726 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
727 0, 4, /* M */
736 0x168, 0, 4, 8, 2, BIT(15), 0);
739 0x180, 0, 4, 24, 3, BIT(31), 0);
741 0x184, 0, 4, 24, 3, BIT(31), 0);
746 0x188, 0, 4, 24, 3, BIT(31), 0);
748 0x18c, 0, 4, 24, 3, BIT(31), 0);
750 0x190, 0, 4, 24, 3, BIT(31), 0);
752 0x194, 0, 4, 24, 3, BIT(31), 0);
755 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
759 { .index = 0, .div = 750, },
773 .reg = 0x1f0,
792 .reg = 0x1f4,
961 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
982 1, 2, 0);
985 1, 2, 0);
988 1, 2, 0);
991 1, 2, 0);
1166 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1167 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1168 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1170 [RST_DRAM] = { 0x0f4, BIT(31) },
1171 [RST_MBUS] = { 0x0fc, BIT(31) },
1173 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
1174 [RST_BUS_CE] = { 0x2c0, BIT(5) },
1175 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
1176 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
1177 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
1178 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
1179 [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
1180 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
1181 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
1182 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
1183 [RST_BUS_TS] = { 0x2c0, BIT(18) },
1184 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
1185 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
1186 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
1187 [RST_BUS_SPI2] = { 0x2c0, BIT(22) },
1188 [RST_BUS_SPI3] = { 0x2c0, BIT(23) },
1189 [RST_BUS_SATA] = { 0x2c0, BIT(24) },
1190 [RST_BUS_OTG] = { 0x2c0, BIT(25) },
1191 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
1192 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
1193 [RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
1194 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
1195 [RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
1196 [RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
1198 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1199 [RST_BUS_MP] = { 0x2c4, BIT(2) },
1200 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1201 [RST_BUS_CSI0] = { 0x2c4, BIT(8) },
1202 [RST_BUS_CSI1] = { 0x2c4, BIT(9) },
1203 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1204 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1205 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1206 [RST_BUS_TVE0] = { 0x2c4, BIT(13) },
1207 [RST_BUS_TVE1] = { 0x2c4, BIT(14) },
1208 [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
1209 [RST_BUS_GMAC] = { 0x2c4, BIT(17) },
1210 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1211 [RST_BUS_TVD0] = { 0x2c4, BIT(21) },
1212 [RST_BUS_TVD1] = { 0x2c4, BIT(22) },
1213 [RST_BUS_TVD2] = { 0x2c4, BIT(23) },
1214 [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
1215 [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
1216 [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) },
1217 [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) },
1218 [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) },
1219 [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) },
1220 [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
1221 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1223 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
1225 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1226 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1227 [RST_BUS_AC97] = { 0x2d0, BIT(2) },
1228 [RST_BUS_IR0] = { 0x2d0, BIT(6) },
1229 [RST_BUS_IR1] = { 0x2d0, BIT(7) },
1230 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1231 [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
1232 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1233 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1234 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1236 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1237 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1238 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1239 [RST_BUS_I2C3] = { 0x2d8, BIT(3) },
1240 [RST_BUS_CAN] = { 0x2d8, BIT(4) },
1241 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
1242 [RST_BUS_PS20] = { 0x2d8, BIT(6) },
1243 [RST_BUS_PS21] = { 0x2d8, BIT(7) },
1244 [RST_BUS_I2C4] = { 0x2d8, BIT(15) },
1245 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1246 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1247 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1248 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1249 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
1250 [RST_BUS_UART5] = { 0x2d8, BIT(21) },
1251 [RST_BUS_UART6] = { 0x2d8, BIT(22) },
1252 [RST_BUS_UART7] = { 0x2d8, BIT(23) },
1286 #define SUN8I_R40_GMAC_CFG_REG 0x164
1299 .max_register = 0x320, /* PLL_LOCK_CTRL_REG */
1306 #define SUN8I_R40_SYS_32K_CLK_REG 0x310
1307 #define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
1316 reg = devm_platform_ioremap_resource(pdev, 0); in sun8i_r40_ccu_probe()
1323 writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG); in sun8i_r40_ccu_probe()
1359 return 0; in sun8i_r40_ccu_probe()