Lines Matching +full:8 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
68 {3, 8},
75 {2, 8},
83 {2, 8},
130 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
136 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
184 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
186 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
206 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
208 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
210 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
212 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
214 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
216 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
218 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
220 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
222 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
224 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
226 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
228 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
230 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
231 BUS_MSTOP(1, BIT(8))),
232 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
239 BUS_MSTOP(8, BIT(2))),
241 BUS_MSTOP(8, BIT(2))),
243 BUS_MSTOP(8, BIT(2))),
245 BUS_MSTOP(8, BIT(2))),
247 BUS_MSTOP(8, BIT(3))),
248 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
249 BUS_MSTOP(8, BIT(3))),
250 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
251 BUS_MSTOP(8, BIT(3))),
253 BUS_MSTOP(8, BIT(3))),
255 BUS_MSTOP(8, BIT(4))),
257 BUS_MSTOP(8, BIT(4))),
259 BUS_MSTOP(8, BIT(4))),
261 BUS_MSTOP(8, BIT(4))),
265 BUS_MSTOP(7, BIT(9))),
268 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
269 BUS_MSTOP(8, BIT(5)), 1),
270 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
271 BUS_MSTOP(8, BIT(5)), 1),
273 BUS_MSTOP(8, BIT(5)), 1),
275 BUS_MSTOP(8, BIT(5)), 1),
277 BUS_MSTOP(8, BIT(5))),
279 BUS_MSTOP(8, BIT(5))),
281 BUS_MSTOP(8, BIT(6)), 1),
283 BUS_MSTOP(8, BIT(6)), 1),
285 BUS_MSTOP(8, BIT(6)), 1),
287 BUS_MSTOP(8, BIT(6)), 1),
289 BUS_MSTOP(8, BIT(6))),
291 BUS_MSTOP(8, BIT(6))),
302 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
303 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
314 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
315 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
316 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
317 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
318 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
319 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
320 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
321 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
322 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
323 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
324 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
325 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
326 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
331 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
332 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */