Lines Matching +full:5 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
121 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
173 BUS_MSTOP(3, BIT(5))),
175 BUS_MSTOP(5, BIT(10))),
177 BUS_MSTOP(5, BIT(11))),
178 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
179 BUS_MSTOP(2, BIT(13))),
181 BUS_MSTOP(2, BIT(14))),
183 BUS_MSTOP(11, BIT(13))),
185 BUS_MSTOP(11, BIT(14))),
187 BUS_MSTOP(11, BIT(15))),
189 BUS_MSTOP(12, BIT(0))),
191 BUS_MSTOP(3, BIT(10))),
193 BUS_MSTOP(3, BIT(10))),
195 BUS_MSTOP(1, BIT(0))),
197 BUS_MSTOP(1, BIT(0))),
199 BUS_MSTOP(5, BIT(12))),
200 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
201 BUS_MSTOP(5, BIT(12))),
202 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
203 BUS_MSTOP(5, BIT(13))),
204 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
205 BUS_MSTOP(5, BIT(13))),
207 BUS_MSTOP(3, BIT(14))),
209 BUS_MSTOP(10, BIT(15))),
211 BUS_MSTOP(10, BIT(15))),
213 BUS_MSTOP(10, BIT(15))),
215 BUS_MSTOP(3, BIT(13))),
217 BUS_MSTOP(1, BIT(1))),
218 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
219 BUS_MSTOP(1, BIT(2))),
221 BUS_MSTOP(1, BIT(3))),
223 BUS_MSTOP(1, BIT(4))),
225 BUS_MSTOP(1, BIT(5))),
227 BUS_MSTOP(1, BIT(6))),
229 BUS_MSTOP(1, BIT(7))),
231 BUS_MSTOP(1, BIT(8))),
233 BUS_MSTOP(4, BIT(5))),
234 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
235 BUS_MSTOP(4, BIT(5))),
236 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
237 BUS_MSTOP(4, BIT(5))),
238 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
239 BUS_MSTOP(8, BIT(2))),
240 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
241 BUS_MSTOP(8, BIT(2))),
242 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
243 BUS_MSTOP(8, BIT(2))),
244 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
245 BUS_MSTOP(8, BIT(2))),
246 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
247 BUS_MSTOP(8, BIT(3))),
248 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
249 BUS_MSTOP(8, BIT(3))),
250 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
251 BUS_MSTOP(8, BIT(3))),
252 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
253 BUS_MSTOP(8, BIT(3))),
254 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
255 BUS_MSTOP(8, BIT(4))),
256 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
257 BUS_MSTOP(8, BIT(4))),
258 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
259 BUS_MSTOP(8, BIT(4))),
260 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
261 BUS_MSTOP(8, BIT(4))),
262 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
263 BUS_MSTOP(7, BIT(7))),
264 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
265 BUS_MSTOP(7, BIT(9))),
266 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
267 BUS_MSTOP(7, BIT(10))),
268 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
269 BUS_MSTOP(8, BIT(5)), 1),
270 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
271 BUS_MSTOP(8, BIT(5)), 1),
272 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
273 BUS_MSTOP(8, BIT(5)), 1),
274 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
275 BUS_MSTOP(8, BIT(5)), 1),
276 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
277 BUS_MSTOP(8, BIT(5))),
278 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
279 BUS_MSTOP(8, BIT(5))),
280 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
281 BUS_MSTOP(8, BIT(6)), 1),
282 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
283 BUS_MSTOP(8, BIT(6)), 1),
285 BUS_MSTOP(8, BIT(6)), 1),
287 BUS_MSTOP(8, BIT(6)), 1),
289 BUS_MSTOP(8, BIT(6))),
291 BUS_MSTOP(8, BIT(6))),
293 BUS_MSTOP(3, BIT(4))),
295 BUS_MSTOP(3, BIT(4))),
297 BUS_MSTOP(3, BIT(4))),
311 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
312 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
316 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
335 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
336 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
337 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */