Lines Matching +full:5 +full:- +full:6
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
16 #include "rzv2h-cpg.h"
99 {2, 6},
102 {5, 12},
103 {6, 14},
170 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
235 BUS_MSTOP(3, BIT(5))),
237 BUS_MSTOP(5, BIT(10))),
239 BUS_MSTOP(5, BIT(11))),
240 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
242 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
261 BUS_MSTOP(5, BIT(12))),
262 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16,
263 BUS_MSTOP(5, BIT(12))),
264 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
265 BUS_MSTOP(5, BIT(13))),
266 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
267 BUS_MSTOP(5, BIT(13))),
280 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
282 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
287 BUS_MSTOP(1, BIT(5))),
289 BUS_MSTOP(1, BIT(6))),
295 BUS_MSTOP(4, BIT(5))),
296 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
297 BUS_MSTOP(4, BIT(5))),
298 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
299 BUS_MSTOP(4, BIT(5))),
300 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
302 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
304 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
306 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
308 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
310 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
312 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
314 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
316 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
318 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
320 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
322 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
324 DEF_MOD("usb3_0_aclk", CLK_PLLDTY_DIV8, 10, 15, 5, 15,
326 DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
328 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
330 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
332 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
334 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
335 BUS_MSTOP(8, BIT(5)), 1),
336 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
337 BUS_MSTOP(8, BIT(5)), 1),
338 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
339 BUS_MSTOP(8, BIT(5)), 1),
340 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
341 BUS_MSTOP(8, BIT(5)), 1),
342 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
343 BUS_MSTOP(8, BIT(5))),
344 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
345 BUS_MSTOP(8, BIT(5))),
346 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
347 BUS_MSTOP(8, BIT(6)), 1),
348 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
349 BUS_MSTOP(8, BIT(6)), 1),
350 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
351 BUS_MSTOP(8, BIT(6)), 1),
352 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
353 BUS_MSTOP(8, BIT(6)), 1),
354 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2,
355 BUS_MSTOP(8, BIT(6))),
356 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
357 BUS_MSTOP(8, BIT(6))),
358 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
360 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
362 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
364 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
365 BUS_MSTOP(9, BIT(5))),
366 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
367 BUS_MSTOP(9, BIT(5))),
368 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
369 BUS_MSTOP(9, BIT(5))),
376 DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP, 14, 5, 7, 5,
406 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */
407 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */
408 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
413 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
414 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
415 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
418 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
419 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
438 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
439 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
440 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
441 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
442 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
443 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
444 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
445 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
446 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
447 DEF_RST(13, 1, 6, 2), /* ISP_0_VIN_ARESETN */
448 DEF_RST(13, 2, 6, 3), /* ISP_0_REG_ARESETN */
449 DEF_RST(13, 3, 6, 4), /* ISP_0_ISP_SRESETN */
450 DEF_RST(13, 4, 6, 5), /* ISP_0_PRESETN */
451 DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
452 DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
453 DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
454 DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
455 DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
456 DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */