Lines Matching +full:10 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
91 {1, 10},
173 BUS_MSTOP(3, BIT(5))),
175 BUS_MSTOP(5, BIT(10))),
177 BUS_MSTOP(5, BIT(11))),
179 BUS_MSTOP(2, BIT(13))),
181 BUS_MSTOP(2, BIT(14))),
183 BUS_MSTOP(11, BIT(13))),
185 BUS_MSTOP(11, BIT(14))),
187 BUS_MSTOP(11, BIT(15))),
188 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
189 BUS_MSTOP(12, BIT(0))),
191 BUS_MSTOP(3, BIT(10))),
193 BUS_MSTOP(3, BIT(10))),
195 BUS_MSTOP(1, BIT(0))),
197 BUS_MSTOP(1, BIT(0))),
199 BUS_MSTOP(5, BIT(12))),
201 BUS_MSTOP(5, BIT(12))),
203 BUS_MSTOP(5, BIT(13))),
205 BUS_MSTOP(5, BIT(13))),
207 BUS_MSTOP(3, BIT(14))),
209 BUS_MSTOP(10, BIT(15))),
211 BUS_MSTOP(10, BIT(15))),
213 BUS_MSTOP(10, BIT(15))),
215 BUS_MSTOP(3, BIT(13))),
217 BUS_MSTOP(1, BIT(1))),
219 BUS_MSTOP(1, BIT(2))),
221 BUS_MSTOP(1, BIT(3))),
223 BUS_MSTOP(1, BIT(4))),
225 BUS_MSTOP(1, BIT(5))),
227 BUS_MSTOP(1, BIT(6))),
228 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
229 BUS_MSTOP(1, BIT(7))),
231 BUS_MSTOP(1, BIT(8))),
233 BUS_MSTOP(4, BIT(5))),
234 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
235 BUS_MSTOP(4, BIT(5))),
236 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
237 BUS_MSTOP(4, BIT(5))),
238 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
239 BUS_MSTOP(8, BIT(2))),
240 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
241 BUS_MSTOP(8, BIT(2))),
242 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
243 BUS_MSTOP(8, BIT(2))),
244 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
245 BUS_MSTOP(8, BIT(2))),
246 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
247 BUS_MSTOP(8, BIT(3))),
248 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
249 BUS_MSTOP(8, BIT(3))),
250 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
251 BUS_MSTOP(8, BIT(3))),
252 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
253 BUS_MSTOP(8, BIT(3))),
254 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
255 BUS_MSTOP(8, BIT(4))),
256 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
257 BUS_MSTOP(8, BIT(4))),
258 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
259 BUS_MSTOP(8, BIT(4))),
260 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
261 BUS_MSTOP(8, BIT(4))),
263 BUS_MSTOP(7, BIT(7))),
265 BUS_MSTOP(7, BIT(9))),
267 BUS_MSTOP(7, BIT(10))),
269 BUS_MSTOP(8, BIT(5)), 1),
271 BUS_MSTOP(8, BIT(5)), 1),
272 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
273 BUS_MSTOP(8, BIT(5)), 1),
275 BUS_MSTOP(8, BIT(5)), 1),
277 BUS_MSTOP(8, BIT(5))),
279 BUS_MSTOP(8, BIT(5))),
281 BUS_MSTOP(8, BIT(6)), 1),
283 BUS_MSTOP(8, BIT(6)), 1),
285 BUS_MSTOP(8, BIT(6)), 1),
287 BUS_MSTOP(8, BIT(6)), 1),
289 BUS_MSTOP(8, BIT(6))),
291 BUS_MSTOP(8, BIT(6))),
293 BUS_MSTOP(3, BIT(4))),
295 BUS_MSTOP(3, BIT(4))),
297 BUS_MSTOP(3, BIT(4))),
303 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
320 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
321 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
327 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
328 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
329 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
330 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
331 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
332 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
333 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
334 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
335 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */