Lines Matching +full:1 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
65 {0, 1},
66 {1, 2},
74 {1, 4},
82 {1, 4},
91 {1, 10},
119 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
120 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
121 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
122 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
129 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
130 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
131 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
134 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
135 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
136 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
138 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
139 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
152 DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
161 DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
162 DEF_FIXED("usb2_0_clk_core0", R9A09G056_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
164 CLK_PLLETH_DIV_125_FIX, 1, 1),
166 CLK_PLLETH_DIV_125_FIX, 1, 1),
167 DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
172 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
186 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
195 BUS_MSTOP(1, BIT(0))),
197 BUS_MSTOP(1, BIT(0))),
202 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17,
208 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
210 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
212 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
214 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
216 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
217 BUS_MSTOP(1, BIT(1))),
218 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
219 BUS_MSTOP(1, BIT(2))),
220 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
221 BUS_MSTOP(1, BIT(3))),
222 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
223 BUS_MSTOP(1, BIT(4))),
224 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
225 BUS_MSTOP(1, BIT(5))),
226 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
227 BUS_MSTOP(1, BIT(6))),
228 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
229 BUS_MSTOP(1, BIT(7))),
230 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
231 BUS_MSTOP(1, BIT(8))),
232 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
236 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
250 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
265 BUS_MSTOP(7, BIT(9))),
269 BUS_MSTOP(8, BIT(5)), 1),
270 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
271 BUS_MSTOP(8, BIT(5)), 1),
273 BUS_MSTOP(8, BIT(5)), 1),
275 BUS_MSTOP(8, BIT(5)), 1),
281 BUS_MSTOP(8, BIT(6)), 1),
283 BUS_MSTOP(8, BIT(6)), 1),
285 BUS_MSTOP(8, BIT(6)), 1),
286 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
287 BUS_MSTOP(8, BIT(6)), 1),
294 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
301 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
302 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
303 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
307 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
308 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
315 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
316 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
317 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
318 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
319 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
320 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
321 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
322 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
323 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
324 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
325 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
326 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
332 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
336 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
337 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */